Rainbow Electronics ATmega8HVD - Manual (Page 36)

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8052B–AVR–09/08
ATmega4HVD/8HVD
9.7.3 On-chip Debug System
A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep
modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse
should be disabled when debugWire is not used.
9.7.4 Battery Protection
If one of the Battery Protection features is not needed by the application, this feature should be
disabled, see
”BPCR – Battery Protection Control Register” on page 109 . The current con-
sumption in the Battery Protection circuitry is only significant in Power-save mode. Disabling
both FETs will automatically disable the Battery Protection module in order to save power.
9.7.5 ADC
If enabled, the ADC will consume power independent of sleep mode. To save power, the ADC
should be disabled when not used, and before entering Power-save sleep mode. See
”ADC -
Analog-to-Digital Converter” on page 90 for details on ADC operation. When PB0 is used as
ADC0, the digital input buffer of this pin should be disabled by setting the PB0DID bit in the
DIDR0 register.
9.7.6 FET Driver
To minimize the power consumption in Power-save mode, the DUVR mode of the FET Driver
should be disabled to make sure that the Fast RC Oscillator is stopped.
9.8 Register Description
9.8.1 SMCR – Sleep Mode Control Register
The Sleep Mode Control Register contains control bits for power management.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved bits in the ATmega4HVD/8HVD, and will always read as zero.
• Bits 3:1 – SM2:0: Sleep Mode Select Bits 2, 1 and 0
These bits select between the four available sleep modes as shown in Table 9-3 .
Bit 7 6 5 4 3 2 1 0
– – – – SM2 SM1 SM0 SE SMCR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 9-3. Sleep Mode Select
SM2 SM1 SM0 Sleep Mode
0 0 0 Idle
0 0 1 ADC Noise Reduction
0 1 0 Reserved
0 1 1 Power-save
1 0 0 Power-off