Rainbow Electronics ATmega8HVD - Manual (Page 53)

53
8052B–AVR–09/08
ATmega4HVD/8HVD
12. External Interrupt
The External Interrupts are triggered by the INT1:0 pins. Observe that, if enabled, the interrupt
will trigger even if the INT1:0 pins are configured as outputs. This feature provides a way of
generating a software interrupt. The External Interrupts can be triggered by a falling or rising
edge or a low level. This is set up as indicated in the specification for the
”EICRA – External
Interrupt Control Register A” on page 53 . When the external interrupt is enabled and is config-
ured as level triggered, the interrupt will trigger as long as the pin is held low. A interrupt is
detected asynchronously. This implies that the interrupt can be used for waking the part also
from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle
mode.
Note that if a level triggered interrupt is used for wake-up from Power-save mode, the changed
level must be held for some time to wake up the MCU. This makes the MCU less sensitive to
noise. The changed level is sampled twice by the ULP Oscillator clock. The period of the ULP
Oscillator is 7.8 µs (nominal) at 25
°
C. The MCU will wake up if the input has the required level
during this sampling or if it is held until the end of the start-up time. The start-up time is defined
by the SUT fuses as described in
”Clock Systems and their Distribution” on page 22 . If the
level is sampled twice by the Slow RC Oscillator clock but disappears before the end of the
start-up time, the MCU will still wake up, but no interrupt will be generated. The required level
must be held long enough for the MCU to complete the wake up to trigger the level interrupt.
12.1 Register Description
12.1.1 EICRA – External Interrupt Control Register A
• Bits 7:4 – RES: Reserved Bits
These bits are reserved in the ATmega4HVD/8HVD, and will always read as zero.
• Bits 3:0 – ISC11, ISC10 - ISC01, ISC00: External Interrupt 1 - 0 Sense Control Bits
The External Interrupts 1- 0 are activated by the external pins INT1:0 if the SREG I-flag and
the corresponding interrupt mask in the EIMSK is set. The level and edges on the external
pins that activate the interrupt is defined in
Table 12-1 on page 54 . Edges on INT1:0 are regis-
tered asynchronously. Pulses on the INT1:0 pins wider than the minimum pulse width given in
”External Interrupts Characteristics” on page 144 will generate an interrupt. Shorter pulses are
not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be
held until the completion of the currently executing instruction to generate an interrupt. If
enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held
low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first
disable INTnby clearing its Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can
Bit 7 6 5 4 3 2 1 0
- - - - ISC11 ISC10 ISC01 ISC00 EICRA
Read/Write R R R R R/W RR/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0