Rainbow Electronics ATmega8HVD - Manual (Page 48)

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8052B–AVR–09/08
ATmega4HVD/8HVD
10.8 Register Description
10.8.1 MCUSR – MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bits 7:4, 2 – Res: Reserved Bits
These bits are reserved, and will always read as zero.
• Bit 4 – OCDRF: OCD Reset Flag
This bit is set if a debugWIRE Reset occurs. This bit is reset by a Power-on Reset, or by writ-
ing a logic zero to the flag.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing
a logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the
flag.
To make use of the Reset flags to identify a reset condition, the user should read and then
reset the MCUSR as early as possible in the program. If the register is cleared before another
reset occurs, the source of the reset can be found by examining the reset flags.
10.8.2 WDTCSR – Watchdog Timer Control Register
• Bit 7 - WDIF: Watchdog Interrupt Flag
This bit is set when a timeout occurs in the Watchdog Timer and the Watchdog Timer is con-
figured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit
in SREG and WDIE are set, the Watchdog Timeout Interrupt is executed.
• Bit 6 - WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt
is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Inter-
rupt Mode, and the corresponding interrupt is executed if timeout in the Watchdog Timer
occurs.
Bit 7 6 5 4 3 2 1 0
– – – OCDRF WDRF – EXTRF PORF MCUSR
Read/Write R R R R/W R/W R R/W R/W
Initial Value 0 0 0 0 (1) 0 (1) (1)
Bit 7 6 5 4 3 2 1 0
WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCSR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 X 0 0 0