Rainbow Electronics ATmega8HVD - Manual (Page 132)

132
8052B–AVR–09/08
ATmega4HVD/8HVD
The minimum low and high periods for the serial clock (SCK) input are defined as follows:
Low: > 2.2 CPU clock cycles for f
ck
< 12 MHz, 3 CPU clock cycles for f
ck
>= 12 MHz
High: > 2.2 CPU clock cycles for f
ck
< 12 MHz, 3 CPU clock cycles for f
ck
>= 12 MHz
24.6.1 Serial Programming Algorithm
When writing serial data to the ATmega4HVD/8HVD, data is clocked on the rising edge of
SCK.
When reading data from the ATmega4HVD/8HVD, data is clocked on the falling edge of SCK.
See
Figure 26-1 and Figure 26-2 for timing details.
To program and verify the ATmega4HVD/8HVD in the Serial Programming mode, the follow-
ing sequence is recommended (see four byte instruction formats in
Table 24-10 ):
1. Power-up sequence:
Apply minimum 3V between VFET and GND, and BATT and GND while RESET and
SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is
held low during power-up. In this case, RESET must be given a positive pulse of at
least two CPU clock cycles duration after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of syn-
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
a time by supplying the 5 LSB of the address and data together with the Load Program
memory Page instruction. To ensure correct loading of the page, the data low byte
must be loaded before data high byte is applied for a given address. The Program
memory Page is stored by loading the Write Program memory Page instruction with the
6 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at least
t
WD_FLASH
before issuing the next page. (See Table 24-9 .) Accessing the serial pro-
gramming interface before the Flash write operation completes can result in incorrect
programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling (RDY/BSY) is not used,
the user must wait at least t
WD_EEPROM
before issuing the next byte. (See Table 24-9 .) In
a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is
loaded one byte at a time by supplying the 2 LSB of the address and data together with
the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored
by loading the Write EEPROM Memory Page Instruction with the 6 MSB of the
Table 24-8. Pin Mapping Serial Programming
Symbol Pins I/O Description
SCK PB1 I Serial Clock
MISO PB2 O Serial Data out
MOSI PC1 I Serial Data in