Rainbow Electronics ATmega8HVD - Manual (Page 27)

27
8052B–AVR–09/08
ATmega4HVD/8HVD
8.12 OSI – Oscillator Sampling Interface
8.12.1 Features
• Runtime selectable oscillator input (Slow RC or ULP RC Oscillator)
• 7 bit prescaling of the selected oscillator
• Software read access to the phase of the prescaled clock
• Input capture trigger source for Timer/Counter0
8.12.2 Overview
The Oscillator Sampling Interface (OSI) enables sampling of the Slow RC and Ultra Low
Power RC (ULP) oscillators in ATmega4HVD/8HVD. OSI can be used to calibrate the Fast RC
Oscillator runtime with high accuracy. OSI can also provide an accurate reference for compen-
sating the ULP Oscillator frequency drift.
The prescaled oscillator phase can be continuously read by the CPU through the OSICSR
register. In addition, the input capture function of Timer/Counter0 can be set up to trigger on
the rising edge of the prescaled clock. This enables accurate measurements of the oscillator
frequencies relative to the Fast RC Oscillator.
A simplified block diagram of the Oscillator Sampling Interface is shown in Figure 8-2 .
Figure 8-2. Oscillator Sampling Interface Block Diagram.
Note: 1. One prescaled Slow RC/ULP oscillator period corresponds to 128 times the actual Slow
RC/ULP oscillator period.
The osi_posedge signal pulses on each rising edge of the prescaled Slow RC/ ULP oscillator
clock. This signal is not directly accessible by the CPU, but can be used to trigger the input
capture function of Timer/Counter0. Using OSI in combination with the input capture function
of Timer/Counter0 facilitates accurate measurement of the oscillator frequencies with a mini-
mum of CPU calculation. Refer to
”Timer/Counter(T/C0,T/C1)” on page 74 for details on how
to enable the Input Capture function.
osi_posedge
Databus
Ultra Low
Power RC
Oscillator
Slow RC
Oscillator
O
S
CIL
L
AT
O
R
SELECT
7 bit prescaler
Edge
Detector
OSISEL0
OSICSR
Fast RC
Oscillator
(1)