Rainbow Electronics ATmega8HVD - Manual (Page 62)

62
8052B–AVR–09/08
ATmega4HVD/8HVD
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
14.2 Low Voltage Ports as General Digital I/O
The low voltage ports are bi-directional I/O ports with optional internal pull-ups. Figure 14-2
shows a functional description of one I/O-port pin, here generically called Pxn.
Figure 14-2. General Low Voltage Digital I/O (1)
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
I/O
,
SLEEP, and PUD are common to all ports.
14.2.1 Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in ”Regis-
ter Description” on page 70 , the DDxn bits are accessed at the DDRx I/O address, the
PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has
to be configured as an output pin. The port pins are tri-stated when reset condition becomes
active, even if no clocks are running.
clk
RPx
RRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clk
I/O
: I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
RESET
RESET
Q
Q D
Q
Q D
CLR
PORTxn
Q
Q D
CLR
DDxn
PINxn
D
ATA
B
U
S
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
WPx
0
1
WRx
WPx: WRITE PINx REGISTER