Rainbow Electronics ATmega8HVD - Manual (Page 89)

89
8052B–AVR–09/08
ATmega4HVD/8HVD
• Bit 2 – OCFnB: Output Compare Flag n B
The OCFnB bit is set when a Compare Match occurs between the Timer/Counter and the data
in OCRnB – Output Compare Register n B. OCFnB is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCFnB is cleared by writing a logic
one to the flag. When the I-bit in SREG, OCIEnB (Timer/Counter Compare B Match Interrupt
Enable), and OCFnB are set, the Timer/Counter Compare Match Interrupt is executed.
The OCFnB is not set in 16-bit Output Compare mode when the Output Compare Register
OCRnB is used as the high byte of the 16-bit Output Compare Register or in 16-bit Input Cap-
ture mode when the Output Compare Register OCRnB is used as the high byte of the Input
Capture Register.
• Bit 1– OCFnA: Output Compare Flag n A
The OCFnA bit is set when a Compare Match occurs between the Timer/Counter n and the
data in OCRnA – Output Compare Register n. OCFnA is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCFnA is cleared by writing a logic
one to the flag. When the I-bit in SREG, OCIEnA (Timer/Counter n Compare Match Interrupt
Enable), and OCFnA are set, the Timer/Counter n Compare Match Interrupt is executed.
The OCFnA is also set in 16-bit mode when a Compare Match occurs between the
Timer/Counter n and 16-bit data in OCRnB/A. The OCFnA is not set in Input Capture mode
when the Output Compare Register OCRnA is used as an Input Capture Register.
• Bit 0 – TOVn: Timer/Counter n Overflow Flag
The bit TOVn is set when an overflow occurs in Timer/Counter n. TOVn is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, TOVn is
cleared by writing a logic one to the flag. When the SREG I-bit, TOIEn (Timer/Counter n Over-
flow Interrupt Enable), and TOVn are set, the Timer/Counter n Overflow interrupt is executed.