Rainbow Electronics ATmega8HVD - Manual (Page 17)

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8052B–AVR–09/08
ATmega4HVD/8HVD
tions. Refer to the instruction set section for more details. When using the I/O specific
commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these
addresses. The ATmega4HVD/8HVD is a complex microcontroller with more peripheral units
than can be supported within the 64 location reserved in Opcode for the IN and OUT instruc-
tions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can there-
fore be used on registers containing such status flags. The CBI and SBI instructions work with
registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
The ATmega4HVD/8HVD contains three General Purpose I/O Registers. These registers can
be used for storing any information, and they are particularly useful for storing global variables
and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are
directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
7.6 Register Description
7.6.1 EEARL – The EEPROM Address Register
• Bits 7:0 – EEAR7:0: EEPROM Address
The EEPROM Address Registers – EEARL specify the EEPROM address in the 256 bytes
EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 255. The
initial value of EEARL is undefined. A proper value must be written before the EEPROM may
be accessed.
7.6.2 EEDR – The EEPROM Data Register
• Bits 7:0 – EEDR7:0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEARL Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEARL.
Bit 7 6 5 4 3 2 1 0
EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value X X X X X X X X
Bit 7 6 5 4 3 2 1 0
MSB LSB EEDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0