Rainbow Electronics ATmega8HVD - Manual (Page 80)

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8052B–AVR–09/08
ATmega4HVD/8HVD
16.6.2 Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The
noise canceler input is monitored over four samples, and all four must be equal for changing
the output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in
Timer/Counter Control Register n B (TCCRnB). When enabled the noise canceler introduces
additional four system clock cycles of delay from a change applied to the input, to the update
of the ICRn Register. The noise canceler uses the system clock and is therefore not affected
by the prescaler.
The noise canceller should only be used for ICP01 (Port PC0).
16.6.3 Using the Input Capture Unit
The main challenge when using the Input Capture unit is to assign enough processor capacity
for handling the incoming events. The time between two events is critical. If the processor has
not read the captured value in the ICRn Register before the next event occurs, the ICRn will
be overwritten with a new value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICRn Register should be read as early in the inter-
rupt handler routine as possible. The maximum interrupt response time is dependent on the
maximum number of clock cycles it takes to handle any of the other interrupt requests.
Measurement of an external signal duty cycle requires that the trigger edge is changed after
each capture. Changing the edge sensing must be done as early as possible after the ICRn
Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be
cleared by software (writing a logical one to the I/O bit location). For measuring frequency
only, the trigger edge change is not required.
Notes: 1. See ”OSI – Oscillator Sampling Interface” on page 27 for details.
2. The noise canceller cannot be used with this setting.
Note: 1. The noise canceller cannot be used with this setting.
16.7 Output Compare Unit
The comparator continuously compares the Timer/Counter (TCNTn) with the Output Compare
Registers (OCRnA and OCRnB), and whenever the Timer/Counter equals to the Output Com-
pare Regisers, the comparator signals a match. A match will set the Output Compare Flag at
the next timer clock cycle. In 8-bit mode the match can set either the Output Compare Flag
OCFnA or OCFnB, but in 16-bit mode the match can set only the Output Compare Flag
Table 16-3. Timer/Counter0 Input Capture Source (ICS)
ICS0 Source
0 ICP00: osi_posedge pin from OSI module (1) (2)
1 ICP01: Port PC0
Table 16-4. Timer/Counter1 Input Capture Source (ICS)
ICS1 Source
0 ICP10: Battery Protection Interrupt (1)
1 ICP11: Voltage Regulator Interrupt (1)