Rainbow Electronics ATmega8HVD - Manual (Page 35)

35
8052B–AVR–09/08
ATmega4HVD/8HVD
9.5 Power-off Mode
When the SM2:0 bits are written to 100 and the SE bit is set, the SLEEP instruction makes the
CPU shut down the Voltage Regulator, leaving only the Charger Detect Circuitry operational.
To ensure that the MCU enters Power-off mode only when intended, the SLEEP instruction
must be executed within 4 clock cycles after the SM2:0 bits are written. The MCU will reset
when returning from Power-off mode.
Notes: 1. Before entering Power-off sleep mode, interrupts should be disabled by software. Otherwise
interrupts may prevent the SLEEP instruction from being executed within the time limit.
2. Before entering power-off mode, make sure that no EEPROM write sequence is ongoing.
Any ongoing write operation will be aborted when Power-off sleep mode is entered.
9.6 Power Reduction Register
The Power Reduction Register (PRR), see ”PRR0 – Power Reduction Register 0” on page 37 ,
provides a method to stop the clock to individual peripherals to reduce power consumption.
The current state of the peripheral is frozen and the I/O registers can not be read or written.
Resources used by the peripheral when stopping the clock will remain occupied, hence the
peripheral should in most cases be disabled before stopping the clock. Waking up a module,
which is done by clearing the bit in PRR, puts the module in the same state as before
shutdown.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall
power consumption. In all other sleep modes, the clock is already stopped.
9.7 Minimizing Power Consumption
There are several issues to consider when trying to minimize the power consumption in an
AVR controlled system. In general, sleep modes should be used as much as possible, and the
sleep mode should be selected so that as few as possible of the device’s functions are operat-
ing. All functions not needed should be disabled. In particular, the following modules may need
special consideration when trying to achieve the lowest possible power consumption.
9.7.1 Watchdog Timer
If the Watchdog Timer is not needed in the application, the module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes except Power-off. The
Watchdog Timer current consumption is significant only in Power-save mode. Refer to
”Watchdog Timer” on page 45 for details on how to configure the Watchdog Timer.
9.7.2 Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important is then to ensure that no pins drive resistive loads. In sleep modes where both
the I/O clock (clk
I/O
) and the ADC clock (clk
ADC
) are stopped, the input buffers of the device will
be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section
”Digital Input Enable and Sleep Modes” on page 65 for details on
which pins are enabled. If the input buffer is enabled and the input signal is left floating or have
an analog signal level close to VCC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to VCC/2 on an input pin can cause significant current even in active mode. Digital
input buffers can be disabled by writing to the Digital Input Disable Register. Refer to
”DIDR0 –
Digital Input Disable Register 0” on page 98 for details.