HP A7818-IE002 - Manual (Page 59)

System Board
System Bus
Chapter 2 59
• Dual independent bus architecture, which combines a dedicated 64-bit Level 2 cache
bus (supporting 256KB), plus a 64-bit system bus that enables multiple
simultaneous transactions
• MMX2 technology, which gives higher performance for media
communications, and 3D applications
• Dynamic execution to speed up software performance
• Internet Streaming SIMD Extensions 2 (SSE2) for enhanced floating point and 3D
application performance
• Uses multiple low-power states, such as AutoHALT, Stop-Grant, Sleep, and Deep
Sleep to conserve power during idle times
The Pentium IV processor is packaged in a pin grid array (PGA) that fits into a PGA423
socket (423-pin Zero Insertion Force—ZIF—socket).
Processor Clock
The 100MHz system bus clock is provided by a PLL. The processor core clock is derived
from the system bus by applying a ratio. This ratio is fixed in the processor. The
processor then applies this ratio to the system bus clock to generate its CPU core
frequency.
Bus Frequencies
The system board contains a 14.318MHz crystal oscillator. This frequency is multiplied
to 133MHz by a phase-locked loop. An internal clock multiplier within the processor
further scales this number.
The bus frequency and the processor voltage are set automatically.
Voltage Regulation Module (VRM)
One VRM is integrated on the system board, complying with VRM specification 9.0. The
system supports high-current and low-voltage processors.
The processor requires a dedicated power voltage to supply the CPU core and Level 2
cache. The processor codes through Voltage Identification (VID) pins with a required
voltage level of 1.30V to 2.05V. The VID set is decoded by the VRM on the system board
that in return supplies the required power voltage to the processor. Note, however, that
voltage may vary from one processor model to another.
Cache Memory
The Pentium IV integrates the following cache memories on the same die as the
processor cache:
• A trace instruction and Level 1 data cache. The trace cache is 4-way set associative.
• A 256KB Level 2 cache. The Level 2 cache is 8-way associative.
Intel sets the amount of cache memory at the time of manufacture. You can’t change the
value.