HP A7818-IE002 - Manual (Page 41)

System Board
Memory Controller Hub (82850)
Chapter 2 41
32-bit for AGP and AGP/PCI transactions. The MCH contains a 32-deep AGP Requests
queue. High priority accesses are supported. All accesses from the AGP interface that
fall within the graphic aperture address range pass through an address translation
mechanism with a fully associative 20 entry TLB. Accesses between AGP and the hub
interface are limited to memory writes originating from the hub interface for the AGP
bus.
The AGP interface is clocked from a dedicated 66 MHz clock (661N). The
AGP-to-host/core interface is asynchronous. The AGP buffers operate only in 1.5V mode.
They are not 3.3V safe.
Hub Interface
The 8-bit hub interface connects the MCH to the ICH2. Most communications between
the MCH and the ICH2 occur over this interface. The hub interface runs at 66 MHz/266
MB/s.
The hub interface’s supported traffic types include: hub interface-to -AGP memory
writes, hub interface-to-DRAM, processor-to-hub interface, messaging (MSI interrupt
messages, power management state change, MI, SCI, and SERR error indication). It is
assumed that the hub interface is always connected to an ICH2.
RDRAM Interface
The MCH directly supports two channels of Direct RDRAM memory operating in
lock-step using RSL technology. These channels run at 300 MHz and 400MHz and
support 128 Mb and 256 Mb technology RDRAM Direct devices. These 128 Mb and 256
Mb RDRAMs use page sizes of 1 Kb, while 256 Mb devices may also be configured to use
2 Kb pages. A maximum of 64 RDRAM devices are supported on the paired channels
without external logic (128Mbit technology implies 1GB maximum in 32MB increments,
whereas 256Mbit technology implies 2GB maximum in 64MB increments).
The MCH also provides optional ECC error checking for RDRAM data integrity. During
DRAM writes, ECC is generated on a QWord (64-bit) basis. During DRAM reads, and the
read of the data that underlies partial writes, the MCH supports detection of single-bit
and multiple-bit errors, and will correct single-bit errors when correction is enabled.
RDRAM Thermal Management
The relatively high power dissipation needs of RDRAM necessitate a MCH mechanism
capable of putting a number of memory devices into a power-saving mode to keep an
inadequately cooled system from overheating. RDRAM devices may be in one of three
power-management states: active, standby or “nap.” The MCH implements the RDRAM
nap mode.
Two queues are used in the MCH to control power consumption: the A queue contains
references to device pairs that are currently in the active mode while the B queue
contains references to devices that are in the standby mode. This means that all devices
that are in neither queue are in standby or napping. The A queue can hold from 1 to 8
device pairs, while the B queue can be configured to contain between 1 and 16 device
pairs. This allows power consumption to be tuned.
The MCH also implements a mode in which all devices are turned on and it is assumed
that the system will provide adequate cooling. This means that all devices that are in
neither queue A or B are in standby mode. One fail-safe mechanism is supported that