HP A7818-IE002 - Manual (Page 42)

System Board
Memory Controller Hub (82850)
Chapter 2 42
protects the RDRAM devices from thermal overload. This mechanism polls the thermal
indicator bits in the RDRAM devices themselves. When the mechanism is activated, the
MCH immediately exits the “all devices on” mode and reverts to whatever queue mode
has been programmed by system software.
Dual Rambus Bus
The Dual Rambus bus is comprised of 16 x 2 bits of data information, and eight bits of
Error Correcting Code (ECC). The bus is connected to the RIMM memory slots and to
the MCH chip so that the system supports two Dual Rambus channels (A and B).
Both channels run at 300MHz or 400MHz, supporting as many as 32 Rambus devices
per channel. The maximum available data bandwidth is 3.2GB/s at 400MHz.
The configuration of both primary rambus channels must be symmetrical. The memory
configuration on channel A must be identical to the memory configuration on channel B.
This means that you must install the memory in identical pairs.
RIMM Memory Slots
The HP Workstation x2100 has four RIMM memory sockets for installing two or four
RDRAM memory modules:
• RIMM A1
• RIMM A2
• RIMM B1
• RIMM B2
Figure 2-7 RIMM Memory Slots
Each pair of memory sockets must contain identical memory modules (identical in size,
speed, and type). That is, sockets A1 and B1 must contain identical modules, and sockets
A2 and B2 must contain identical modules (or continuity modules).
If you install only two RDRAM modules, use the sockets marked A1 and B1. The other
two sockets (A2 and B2) must contain continuity modules.
Each RIMM socket is connected to the SMBus.
Read/Write Buffers
The MCH defines a data-buffering scheme to support the required level of concurrent
operations and provide adequate sustained bandwidth between the DRAM subsystem
and all other system interfaces (CPU, AGP, and PCI).