HP A7818-IE002 - Manual (Page 38)

System Board
Memory Controller Hub (82850)
Chapter 2 38
Memory Controller Hub (82850)
The MCH host bridge/controller is contained in a 615-pin Organic Land Grid Array
(OLGA) package and is the bridge between the system bus, Dual Rambus bus (main
memory), AGP 4x (graphic), and Hub Link 8-bit.
Figure 2-6 shows an example of the system block diagram using the MCH.
Figure 2-6 System Block Diagram using MCH
I850 Memory
Controller Hub (MCH)
82850
Dual Rambus
Address (36)
Control
Data (64)
AGP 4x Bus
133MHz (1 GB
MB/s data transfer
rate)
HUB LINK 8
(266MB/s data
transfer rate)
I/O Controller Hub2
(ICH2) 82801BA
3.2GB/s at 400MHz
data transfer rate
AGP
Inter-
face
Memory
Controller
1.5V
AGP
PRO
connector
Socket 423 Intel Pentium IV
Processor
Four onboard
RIMM sockets
supporting
RDRAM
memory
100MHz two-way system bus
(Data Bus runs at 4 x 100MHz,
3.2GB/s transfer rate)