HP A7818-IE002 - Manual (Page 43)

System Board
Memory Controller Hub (82850)
Chapter 2 43
System Clocking
The MCH has the following clock input pins:
• Differential BCLK0/BCLK1 for the host interface
• 66 MHz clock input for the AGP and hub interface
• Differential CTM/CTM# and CFM/CFM# for each of the two RAC’s.
Clock synthesizer chip(s) are responsible for generating the system host clocks, AGP and
hub interface clocks, PCI clocks and RDRAM clocks. The MCH provides two pairs of
feedback signals to the Direct Rambus Clock Generator (DRCG) chips to keep the host
and RDRAM clocks aligned. The host speed is 100 MHz. The RDRAM speed is 300 MHz
or 400 MHz. The MCH does not require any relationship between the BCLK host clock
and the 66 MHz clock generated for AGP and hub interfaces; they are totally
asynchronous from each other. The AGP and hub interfaces run at a constant 66 MHz
base frequency. The hub interface runs at 4x. AGP transfers may be 1x/2x/4x.