EXFO FTB/IQS-85100G Packet Blazer for FTB-500/IQS-600 - Manual (Page 266)

Test Functions
256 FTB/IQS-85100G
40/100G Advanced - Lanes Mapping & Skew
40/100G Advanced - Lanes Mapping & Skew
Note: Only available with parallel interface.
From the Test menu, tap Functions, 40/100G Advanced, and the Lanes
Mapping & Skew tab.
TX

PCS/Logical Lane, for Ethernet test applications, indicates the PCS
(Ethernet test applications)/Logical (Transport Test applications) lane
markers. To change the PCS/Logical lane order, see
Default/Random/Manual Mapping on page 258.

Skew (Bits) indicates the TX relative delay in bit time for each
PCS/Logical lane. To change the skew values, see Reset/Manual Skew
on page 259.
CAUI/Physical Lane
Indicates the CAUI (Ethernet test applications)/Physical (Transport Test
applications) Lane numbers.
RX

Skew (bits) indicates the delay in bit time between the earliest
PCS/Logical lane and the current lane for the one to zero transition of
the alignment marker sync bits. The received skew accuracy is
±100 bits.

PCS/Logical Lane indicates received PCS/Logical Lane markers.
Note: If a PCS/Logical Lane marker is detected more than once, a red
background is used to highlight all occurrences of this PCS/Logical Lane
marker. Duplicate is also displayed on a red background.