Rainbow Electronics DS26503 - Manual (Page 78)

DS26503 T1/E1/J1 BITS Element
78 of 123
13.1 LIU Operation
The analog AMI/HDB3 waveform off of the E1 line or the AMI/B8ZS waveform off of the T1 line is
transformer-coupled into the RTIP and RRING pins of the DS26503. The user has the option to use
internal termination, software selectable for 75Ω/100Ω/110Ω/120Ω applications, or external termination.
The LIU recovers clock and data from the analog signal and passes it through the jitter attenuation mux.
The DS26503 contains an active filter that reconstructs the analog received signal for the nonlinear losses
that occur in transmission. The receive circuitry also is configurable for various monitor applications. The
device has a usable receive sensitivity of 0dB to -43dB for E1 and 0dB to -36dB for T1, which allows the
device to operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6000 feet (T1) in length. Data from
the framer portion of the part is sent via the jitter attenuation MUX to the wave shaping circuitry and line
driver. The DS26503 will drive the E1 or T1 line from the TTIP and TRING pins via a coupling
transformer. The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or
short-haul (DSX-1) lines for T1.
13.2 LIU Receiver
The DS26503 contains a digital clock recovery system. The DS26503 couples to the receive line via a 1:1
transformer. The DS26503 has the option of using software-selectable termination requiring only a single,
fixed pair of termination resistors.
The DS26503’s LIU is designed to be fully software selectable for E1 and T1 without the need to change
any external resistors for the receive-side. The receiver will allow the user to configure the DS26503 for
75Ω, 100Ω, 110Ω, or 120Ω receive termination by setting the RT0(LIC4.0), RT1(LIC4.1), and
RT2(LIC4.2). When using the internal termination feature, the resistors labeled R in
Figure 13-4 should
be 60Ω each. If external termination is required, RT0, RT1, and RT2 should be set to zero and the
resistors labeled R in
Figure 13-4 will need to be 37.5Ω, 50Ω, 55Ω, or 60Ω each, depending on the line
impedance.
There are two ranges of receive sensitivity for both T1 and E1, which is selectable by the user. The EGL
bit of LIC1 (LIC1.4) selects the full or limited sensitivity.
The resultant E1 or T1 clock derived from MCLK is multiplied by 16 via an internal PLL and fed to the
clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16 times
over-sampler, which is used to recover the clock and data. This over-sampling technique offers
outstanding performance to meet jitter tolerance specifications shown in
Figure 13-6 and Figure 13-7 .
Normally, the clock that is output at the RCLK pin is the recovered clock from the waveform presented at
the RTIP and RRING inputs. If the jitter attenuator is placed in the receive path (as is the case in most
applications), the jitter attenuator restores the RCLK to an approximate 50% duty cycle. If the jitter
attenuator is either placed in the transmit path or is disabled, the RCLK output can exhibit slightly shorter
high cycles of the clock. This is due to the highly over-sampled digital clock recovery circuitry. See the
Receive AC Timing Characteristics section for more details. When no signal is present at RTIP and
RRING, a receive loss of signal (RLOS) condition will occur and the RCLK will be derived from the
JACLK source.
13.2.1 Receive Level Indicator
The DS26503 will report the signal strength at RTIP and RRING in 2.5dB increments via RL3-RL0
located in the Information Register 1 (INFO1). This feature is helpful when trouble shooting line
performance problems.