DS26503 T1/E1/J1 BITS Element
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LIST OF FIGURES
Figure 3-1. Block Diagram ..................................................................................................................... 12
Figure 3-2. Loopback Mux Diagram....................................................................................................... 13
Figure 3-3. Transmit PLL Clock Mux Diagram ....................................................................................... 13
Figure 3-4. Master Clock PLL Diagram.................................................................................................. 14
Figure 13-1. Basic Network Connection................................................................................................. 77
Figure 13-2. Typical Monitor Application................................................................................................ 79
Figure 13-3. CMI Coding ....................................................................................................................... 81
Figure 13-4. Basic Interface................................................................................................................... 90
Figure 13-5. Protected Interface Using Internal Receive Termination .................................................... 91
Figure 13-6. E1 Transmit Pulse Template ............................................................................................. 93
Figure 13-7. T1 Transmit Pulse Template.............................................................................................. 93
Figure 13-8. Jitter Tolerance (T1 Mode) ................................................................................................ 94
Figure 13-9. Jitter Tolerance (E1 Mode) ................................................................................................ 94
Figure 13-10. Jitter Attenuation (T1 Mode) ............................................................................................ 95
Figure 13-11. Jitter Attenuation (E1 Mode) ............................................................................................ 95
Figure 16-1. JTAG Functional Block Diagram........................................................................................ 98
Figure 16-2. TAP Controller State Diagram ......................................................................................... 101
Figure 17-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0 ............................................. 106
Figure 17-2. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 0 ............................................. 106
Figure 17-3. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 1 ............................................. 106
Figure 17-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1 ............................................. 107
Figure 17-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0 ............................................. 107
Figure 17-6. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 0 ............................................. 107
Figure 17-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1 ............................................. 108
Figure 17-8. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 1 ............................................. 108
Figure 19-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00)............................................................. 112
Figure 19-2. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 00).............................................................. 112
Figure 19-3. Motorola Bus Timing (BTS = 1 / BIS[1:0] = 00) ................................................................ 113
Figure 19-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01).............................................................. 115
Figure 19-5. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 01).............................................................. 115
Figure 19-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01)....................................................... 116
Figure 19-7. Motorola Bus Write Timing (BTS = 1 / BIS[1:0] = 01)....................................................... 116
Figure 19-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10 ................................................. 118
Figure 19-9. SPI Interface Timing Diagram, CPHA = 1, BIS[1:0] = 10 ................................................. 118
Figure 19-10. Receive Timing, T1/E1 .................................................................................................. 120
Figure 19-11. Transmit Timing, T1/E1 ................................................................................................. 122
