Rainbow Electronics DS26503 - Manual (Page 3)

DS26503 T1/E1/J1 BITS Element
3 of 123
8. T1 FRAMER/FORMATTER CONTROL REGISTERS ....................................................40
8.1 T1 C
ONTROL
R
EGISTERS
...............................................................................................40
9. E1 FRAMER/FORMATTER CONTROL REGISTERS....................................................46
9.1 E1 C
ONTROL
R
EGISTERS
...............................................................................................46
9.2 E1 I NFORMATION R EGISTERS ..........................................................................................48
10. I/O PIN CONFIGURATION OPTIONS ............................................................................52
11. T1 SYNCHRONIZATION STATUS MESSAGE ..............................................................55
11.1 T1 B
IT
-O
RIENTED
C
ODE
(BOC) C
ONTROLLER
................................................................55
11.2 T RANSMIT BOC.............................................................................................................55
11.3 R
ECEIVE
BOC...............................................................................................................56
12. E1 SYNCHRONIZATION STATUS MESSAGE ..............................................................64
12.1 S
A
/S
I
B
IT
A
CCESS
B
ASED ON
CRC4 M
ULTIFRAME
...........................................................64
12.2 A LTERNATE S A /S I B IT A CCESS B ASED ON D OUBLE -F RAME ...............................................74
13. LINE INTERFACE UNIT (LIU) ........................................................................................77
13.1 LIU O
PERATION
............................................................................................................78
13.2 LIU R ECEIVER ..............................................................................................................78
13.2.1 Receive Level Indicator ...................................................................................................... 78
13.2.2 Receive G.703 Section 10 Synchronization Signal............................................................. 79
13.2.3 Monitor Mode ..................................................................................................................... 79
13.3 LIU T
RANSMITTER
.........................................................................................................79
13.3.1 Transmit Short-Circuit Detector/Limiter............................................................................... 80
13.3.2 Transmit Open-Circuit Detector.......................................................................................... 80
13.3.3 Transmit BPV Error Insertion.............................................................................................. 80
13.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode) .......................................... 80
13.4 MCLK P RE -S CALER ......................................................................................................80
13.5 J
ITTER
A
TTENUATOR
......................................................................................................80
13.6 CMI (C ODE M ARK I NVERSION ) O PTION ...........................................................................81
13.7 LIU C
ONTROL
R
EGISTERS
.............................................................................................82
13.8 R ECOMMENDED C IRCUITS ..............................................................................................90
13.9 C
OMPONENT
S
PECIFICATIONS
........................................................................................92
14. LOOPBACK CONFIGURATION.....................................................................................96
15. 6312KHZ SYNCHRONIZATION INTERFACE................................................................97
15.1 R
ECEIVE
6312
K
H
Z
S
YNCHRONIZATION
I
NTERFACE
O
PERATION
........................................97
15.2 T
RANSMIT
6312
K
H
Z
S
YNCHRONIZATION
I
NTERFACE
O
PERATION
.......................................97
16. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT ...................98
16.1 I
NSTRUCTION
R
EGISTER
...............................................................................................102
16.2 T EST R EGISTERS .........................................................................................................103
16.3 B
OUNDARY
S
CAN
R
EGISTER
.........................................................................................103
16.4 B YPASS R EGISTER ......................................................................................................103
16.5 I
DENTIFICATION
R
EGISTER
............................................................................................103