Rainbow Electronics DS26503 - Manual (Page 12)

DS26503 T1/E1/J1 BITS Element
12 of 123
3. BLOCK DIAGRAMS
Figure 3-1. Block Diagram
RX
LIU
RX
LIU
T1/E1 SSM
FRAMER
CLOCK
- DATA
TX
LIU
T1/E1 SSM
FORMATTER
PLL
CLOCK
MUX
L
O
C
A
L
L
O
O
P
B
A
C
K
M
U
X
PARALLEL/SERIAL CPU I/F
HARDWARE CONTROLLER
RCLK
LOF_CCE
RSER
RS
PLL_OUT
TCLK
TSER
TS
+ DATA
RTIP
RRING
RLOS
RAIS
TTIP
JITTER
ATTENUATOR
CAN BE
ASSIGNED TO
RECEIVE OR
TRANSMIT PATH
OR DISABLED
MASTER CLOCK
MCLK
JTAG PORT TSTRST
TX CLOCK
- DATA
+ DATA
JA
ENABLED
AND IN RX
PATH
JA
ENABLED
AND IN TX
PATH
DS26503
JTAG PORT JTAG PORT JTAG PORT
JTDO JTDI JTCLK JTMS JTRST BIS1 BIS0
JA
ENABLED
AND IN RX
PATH
R
E
M
O
T
E
L
O
O
P
B
A
C
K
M
U
X
PARALLEL,
SERIAL, OR
HARDWARE
CONTROLLER
JA CLOCK