Structured assembly processing – Zilog Z8F0130 User Manual
Page 347

UM013037-1212
Structured Assembly Processing
Zilog Developer Studio II – Z8 Encore!
User Manual
323
•
The
.$CONTINUE
assembler directive is optional. It can be specified an arbitrary
number of times between the
.$WHILE
and
.$WEND
directives.
•
Any valid assembler statement can appear in the statements sections of the structured
assembly test directives. This means, among other things, that structured assembly test
directives can be nested. The structured assembly test directives can be nested up to
255 levels.
•
Nested
.$BREAK
and
.$CONTINUE
directives are associated with the most recent
.$WHILE
directive.
•
There is no preset limit on the number of statements that can appear in the statements
sections; there can be any number of assembler statements in each statements section,
including zero. The operating system file system might impose limitations on file
sizes, and the user must consult the appropriate operating system users guide for such
limitations.
•
The
.$WHILE
and
.$WEND
directives must be coded in matching pairs. That is, it is
not legal to code a
.$WHILE
directive without a matching
.$WEND
directive appearing
later in the source module nor is it legal to code an
.$WEND
directive without a match-
ing
.$WHILE
directive appearing earlier in the source module.
•
The
.$BREAK
and
.$CONTINUE
assembler directives can only appear between
enclosing
.$WHILE
and
.$WEND
directives (or between
.$REPEAT
and
.$UNTIL
directives). It is not valid for the
.$BREAK
and
.$CONTINUE
directives to appear in
any other context.
•
The
.$BREAK
directive has an optional
.$IF
conditional parameter.
•
The
.$CONTINUE
directive has an optional
.$IF
conditional parameter.
•
None of the
.$WHILE
,
.$BREAK
,
.$CONTINUE
, and
.$WEND
assembler directives can
be labeled. If a label is specified, a warning message is issued, and the label is dis-
carded.
Structured Assembly Processing
The following sections describe the assembly-time processing of structured assembly
directives:
•
•
Validity Checks
The following validity checks are performed on the structured assembly block input data.
Unless otherwise specified, violations cause the assembly to fail.
- Z8F0131 Z8F0230 Z8F0231 Z8F0430 Z8F0431 Z8F043A Z8F0830 Z8F0831 Z8F083A Z8F1232 Z8F1233 Z8F0113 Z8F011A Z8F0123 Z8F012A Z8F0213 Z8F021A Z8F0223 Z8F022A Z8F0411 Z8F0412 Z8F0413 Z8F041A Z8F0421 Z8F0422 Z8F0423 Z8F042A Z8F0811 Z8F0812 Z8F0813 Z8F081A Z8F0821 Z8F0822 Z8F0823 Z8F082A Z8F0880 Z8F1621 Z8F1622 Z8F1680 Z8F1681 Z8F1682 Z8F2421 Z8F2422 Z8F2480 Z8F3221 Z8F3222 Z8F3281 Z8F3282 Z8F4821 Z8F4822 Z8F4823 Z8F6081 Z8F6082 Z8F6421 Z8F6422 Z8F6423 Z8F6481 Z8F6482 Z8FS021A ZMOT1AHH Z8FS040B ZMOT0BHH ZMOT0BSB Z8FMC04 Z8FMC08 Z8FMC16