beautypg.com

Glossary – HP XP Performance Advisor Software User Manual

Page 406

background image

Glossary

A

Array Control
Processor (ACP)

ACP is used in the XP disk arrays prior to the XP24000 Disk Array. With the introduction of the
XP24000 Disk Array, the DKA has replaced ACP. The DKA is also applicable for the P9500/XP7
disk arrays.

ACP handles the transfer of data between the cache and the physical drives held in the DKUs.
The ACPs work in pairs, providing a total of eight SCSI buses. Each SCSI bus associated with
one ACP is paired with a SCSI bus on the other ACP pair element. In the event of an ACP failure,
the redundant ACP takes control. Both the ACPs work together by sharing the load. On the XP
models, such as the XP10000 Disk Array, this function is handled by the DKA on the MIX board.

C

Cache

A Cache is a high speed memory that is used to speed up the I/O transaction time. All reads
and writes to the XP and P9500 disk arrays are sent to the cache. The data is buffered in the
cache until it is transferred to the physical disks or from the physical disks (with slower data
throughput) is complete. The benefit of cache memory is that it speeds the I/Os throughput to the
application. The larger the cache size, the greater the amount of data buffering that can occur
and the greater throughput to the applications. In the event of power loss, the battery power
maintains the contents of cache for a specified time period.

Cache Fast Write
(CFW)

The cache fast write is a 3990-3/6 function that can be used with volatile data. It is also a form
of fast write where the subsystem writes the data directly to the cache, which is made available
for later destaging activity.

Cache Logical
Partition (CLPR)

The

cache logical partition contains cache and parity groups. It is also available on the

XP12000,

XP10000, and later generations of the XP/XP7 disk arrays.

NOTE:

CLPR0 always exists (cannot be deleted) and is a pool area for cache and parity groups

that are not yet assigned to other CLPRs.

Cache Memory

The

cache memory stores the read and write information. It is controlled as two areas, one half

in

the CL1 and the other half in the CL2. During a power outage, the information in the cache is

retained

through a battery backup. However, in the newer array models, a forced destage can

occur

prior to that XP/XP7 disk array powering off, depending on the batteries, configuration,

and

so on.

Cache Switch PCB
(CSW)

The CSW PCB has a function to connect the CHA or the DKA to the cache. Each of them is
connected to the cache by the Cache Memory Hierarchical Star Net (C-HSN) method. Each
cluster is provided with two CSWs, and each CSW can connect four cache. The CSW uses an
arbitration to switch any of the cache paths to which the CHA or the DKA must be connected.

CHA

Channel adapter. A device that provides the interface between the array and the external host
system. Occasionally, this term is used synonymously with the term channel host interface processor
(CHIP).

Channel (CH)

Description 1: A path along which signals can be sent; for example, data channel and output
channel.

CHIP

Channel host interface processor. Synonymous with the term CHA.

CHP

Channel processor. The processors located on the CHA. Synonymous with CHIP.

Command Line
User Interface
(CLUI)

In

addition to its GUI, HP XP7 Performance Advisor also provides a command-line utility called

the

CLUI to monitor real-time performance of the XP and the XP7 disk arrays. The CLUI allows

you

to monitor performance, set alarms, and configure host information using commands and

scripts.

You can execute commands in the CLUI and view the same data that is displayed on

the

GUI. The CLUI utility is operating system specific and can be installed locally on the

management

station, or remotely on a client system.

406 Glossary