Intel NETWORK PROCESSOR IXP2800 - Manual (Page 90)

90 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Intel XScale ® Core
3.4.1.2 Operation when Instruction Cache is Disabled
Disabling the cache prevents any lines from being written into the instruction cache. Although the
cache is disabled, it is still accessed and may generate a “hit” if the data is already in the cache.
Disabling the instruction cache does not disable instruction buffering that may occur within the
instruction fetch buffers. Two 8-word instruction fetch buffers will always be enabled in the cache
disabled mode. As instruction fetches continue to “hit” within either buffer (even in the presence of
forward and backward branches), no external fetches for instructions are generated. A miss causes
one or the other buffer to be filled from external memory using the fill policy.
3.4.1.3 Fetch Policy
An instruction-cache “miss” occurs when the requested instruction is not found in the instruction
fetch buffers or instruction cache; a fetch request is then made to external memory. The instruction
cache can handle up to two “misses.” Each external fetch request uses a fetch buffer that holds
32-bytes and eight valid bits, one for each word. A miss causes the following:
1. A fetch buffer is allocated.
2. The instruction cache sends a fetch request to the external bus. This request is for a 32-byte line.
3. Instructions words are returned back from the external bus, at a maximum rate of 1 word per
core cycle. As each word returns, the corresponding valid bit is set for the word in the fetch
buffer.
4. As soon as the fetch buffer receives the requested instruction, it forwards the instruction to the
instruction decoder for execution.
5. When all words have returned, the fetched line will be written into the instruction cache if it is
cacheable and if the instruction cache is enabled. The line chosen for update in the cache is
controlled by the round-robin replacement algorithm. This update may evict a valid line at that
location.
6. Once the cache is updated, the eight valid bits of the fetch buffer are invalidated.
3.4.1.4 Round-Robin Replacement Algorithm
The line replacement algorithm for the instruction cache is round-robin. Each set in the instruction
cache has a round-robin pointer that keeps track of the next line (in that set) to replace. The next
line to replace in a set is the one after the last line that was written. For example, if the line for the
last external instruction fetch was written into way 5-set 2, the next line to replace for that set
would be way 6. None of the other round-robin pointers for the other sets are affected in this case.
After reset, way 31 is pointed to by the round-robin pointer for all the sets. Once a line is written
into way 31, the round-robin pointer points to the first available way of a set, beginning with way0
if no lines have been locked into that particular set. Locking lines into the instruction cache
effectively reduces the available lines for cache updating. For example, if the first three lines of a
set were locked down, the round-robin pointer would point to the line at way 3 after it rolled over
from way 31.