Intel NETWORK PROCESSOR IXP2800 - Manual (Page 12)

12 Hardware Reference Manual
Contents
9 PCI Unit....................................................................................................................................... 319
9.1
Overview........................................................................................................................... 319
9.2 PCI Pin Protocol Interface Block....................................................................................... 321
9.2.1
PCI Commands ................................................................................................... 322
9.2.2 IXP2800 Network Processor Initialization............................................................ 323
9.2.2.1
Initialization by the Intel XScale® Core................................................ 324
9.2.2.2 Initialization by a PCI Host ................................................................... 324
9.2.3 PCI Type 0 Configuration Cycles......................................................................... 325
9.2.3.1
Configuration Write .............................................................................. 325
9.2.3.2 Configuration Read .............................................................................. 325
9.2.4 PCI 64-Bit Bus Extension .................................................................................... 325
9.2.5 PCI Target Cycles................................................................................................ 326
9.2.5.1
PCI Accesses to CSR .......................................................................... 326
9.2.5.2 PCI Accesses to DRAM ....................................................................... 326
9.2.5.3 PCI Accesses to SRAM ....................................................................... 326
9.2.5.4 Target Write Accesses from the PCI Bus ............................................ 326
9.2.5.5 Target Read Accesses from the PCI Bus ............................................ 327
9.2.6 PCI Initiator Transactions .................................................................................... 327
9.2.6.1
PCI Request Operation........................................................................ 327
9.2.6.2 PCI Commands.................................................................................... 328
9.2.6.3 Initiator Write Transactions .................................................................. 328
9.2.6.4 Initiator Read Transactions .................................................................. 328
9.2.6.5 Initiator Latency Timer ......................................................................... 328
9.2.6.6 Special Cycle ....................................................................................... 329
9.2.7 PCI Fast Back-to-Back Cycles............................................................................. 329
9.2.8 PCI Retry ............................................................................................................. 329
9.2.9 PCI Disconnect .................................................................................................... 329
9.2.10 PCI Built-In System Test...................................................................................... 329
9.2.11 PCI Central Functions......................................................................................... 330
9.2.11.1 PCI Interrupt Inputs.............................................................................. 330
9.2.11.2 PCI Reset Output................................................................................. 330
9.2.11.3 PCI Internal Arbiter .............................................................................. 331
9.3 Slave Interface Block ........................................................................................................ 332
9.3.1
CSR Interface ...................................................................................................... 332
9.3.2 SRAM Interface ................................................................................................... 333
9.3.2.1
SRAM Slave Writes ............................................................................. 333
9.3.2.2 SRAM Slave Reads ............................................................................. 334
9.3.3 DRAM Interface ................................................................................................... 334
9.3.3.1
DRAM Slave Writes ............................................................................. 334
9.3.3.2 DRAM Slave Reads ............................................................................. 335
9.3.4 Mailbox and Doorbell Registers........................................................................... 336
9.3.5 PCI Interrupt Pin .................................................................................................. 339
9.4 Master Interface Block ...................................................................................................... 340
9.4.1
DMA Interface...................................................................................................... 340
9.4.1.1
Allocation of the DMA Channels .......................................................... 341
9.4.1.2 Special Registers for Microengine Channels ....................................... 341
9.4.1.3 DMA Descriptor.................................................................................... 342
9.4.1.4 DMA Channel Operation...................................................................... 343
9.4.1.5 DMA Channel End Operation .............................................................. 344
9.4.1.6 Adding Descriptor to an Unterminated Chain ...................................... 344
9.4.1.7 DRAM to PCI Transfer ......................................................................... 344
9.4.1.8 PCI to DRAM Transfer ......................................................................... 345