Intel NETWORK PROCESSOR IXP2800 - Manual (Page 405)

Hardware Reference Manual 405
Intel
®
IXP2800 Network Processor
Performance Monitor Unit
11.4.6.5 PCI Events Target ID(000101) / Design Block #(1000)
110 XG_MSF_WR_3_CPP P_CLK single separate XG msf write length=3 on cpp bus
111 XG_MSF_WR_4_CPP P_CLK single separate XG msf write length=4 on cpp bus
112 XG_PCI_RD_CPP P_CLK single separate XG pci read command on cpp bus
113 XG_PCI_RD_1_CPP P_CLK single separate XG pci read length=1 on cpp bus
114 XG_PCI_RD_8_CPP P_CLK single separate XG pci read length=8 on cpp bus
115 XG_PCI_WR_CPP P_CLK single separate XG pci write command on cpp bus
116 XG_PCI_WR_1_CPP P_CLK single separate XG pci write length=1 on cpp bus
117 XG_PCI_WR_2_CPP P_CLK single separate XG pci write length=2 on cpp bus
118 XG_PCI_WR_3_CPP P_CLK single separate XG pci write length=3 on cpp bus
119 XG_PCI_WR_4_CPP P_CLK single separate XG pci write length=4 on cpp bus
120 XG_CAP_RD_CPP P_CLK single separate XG cap read command on cpp bus
121 XG_CAP_RD_1_CPP P_CLK single separate XG cap read length=1 on cpp bus
122 XG_CAP_RD_8_CPP P_CLK single separate XG cap read length=8 on cpp bus
123 XG_CAP_WR_CPP P_CLK single separate XG cap write command on cpp bus
124 XG_CAP_WR_1_CPP P_CLK single separate XG cap write length=1 on cpp bus
125 reserved
126 reserved
127 reserved
Table 158. Intel XScale ® Core Gasket PMU Event List (Sheet 4 of 4)
Table 159. PCI PMU Event List (Sheet 1 of 5)
Event
Number
Event Name
Clock
Domain
Pulse/
Level
Burst Description
0 PCI_TGT_AFIFO_FULL PCI_CLK single separate PCI Target Address FIFO Full
1 PCI_TGT_AFIFO_NEMPTY P_CLK single separate PCI Target Address FIFO Not Empty
2 PCI_TGT_AFIFO_WR PCI_CLK single separate PCI Target Address FIFO Write
3 PCI_TGT_AFIFO_RD P_CLK single separate PCI Target Address FIFO Read
4 PCI_TGT_RFIFO_FULL P_CLK single separate PCI Target Read FIFO Full
5 PCI_TGT_RFIFO_NEMPTY PCI_CLK single separate PCI Target Read FIFO Not Empty
6 PCI_TGT_RFIFO_WR P_CLK single separate PCI Target Read FIFO Write
7 PCI_TGT_RFIFO_RD PCI_CLK single separate PCI Target Read FIFO Read
8 PCI_TGT_WFIFO_FULL PCI_CLK single separate PCI Target Write FIFO Full
9 PCI_TGT_WFIFO_NEMPTY P_CLK single separate PCI Target Write FIFO Not Empty
10 PCI_TGT_WFIFO_WR PCI_CLK single separate PCI Target Write FIFO Write
11 PCI_TGT_WFIFO_RD P_CLK single separate PCI Target Write FIFO Read
12 PCI_TGT_WBUF_FULL P_CLK single separate PCI Target Write Buffer Full