Intel NETWORK PROCESSOR IXP2800 - Manual (Page 344)

344 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
PCI Unit
9.4.1.5 DMA Channel End Operation
1. Channel owned by PCI:
If not masked via the PCI Outbound Interrupt Mask register, the DMA channel interrupts the
PCI host after the setting of the DMA done bit in the CHAN_X_CONTROL register, which is
readable in the PCI Outbound Interrupt Status register.
2. Channel owned by the Intel XScale
®
core:
If enabled via the Intel XScale
®
core Interrupt Enable registers, the DMA channel interrupts
the Intel XScale
®
core by setting the DMA channel done bit in the CHAN_X_CONTROL
register, which is readable in the Intel XScale
®
core Interrupt Status register.
3. Channel owned by Microengine:
If enabled via the Microengine Auto-Push Enable registers, the DMA channel signals the
Microengine after setting the DMA channel done bit in the CHAN_X_CONTROL register,
which is readable in the Microengine Auto-Push Status register.
9.4.1.6 Adding Descriptor to an Unterminated Chain
It is possible to add a descriptor to a chain while a channel is running. To do so the chain should be
left un-terminated, that is the last descriptor should have End of Chain clear, and the Chain Pointer
value equal to 0. A new descriptor (descriptors) can be added to the chain by overwriting the Chain
Pointer value of the un-terminated descriptor (in SRAM) with the Local Memory address of the
(first) added descriptor (Note that the added descriptor must actually be valid in Local Memory
prior to that). After updating the Chain Pointer field, the software must write a 1 to the Descriptor
Added bit of the Channel Control register. This is necessary for the case where the channel was
paused to reactivate the channel. However, software need not check the state of the channel before
writing that bit; there is no side-effect of writing that bit in the case where the channel had not yet
read the unlinked descriptor.
If the channel was paused or had read an unlinked Pointer, it will re-read the last descriptor
processed (i.e., the one that originally had the 0 value for Chain Pointer) to get the address of the
newly added descriptor.
A descriptor cannot be added to a descriptor that has End of Chain set.
9.4.1.7 DRAM to PCI Transfer
For a DRAM-to-PCI transfer, the DMA channel reads data from DRAM and places it into the
DMA buffer for transfer to the FBus FIFO when the following conditions are met:
• There is at least free space for a read block in the buffer.
• The DRAM controller issues data valid on DRAM push data bus to the DMA engine.
• DMA transfer is not done.
Before data is stored into the DMA buffer, the DRAM starting address is evaluated. Extra data will
be discarded in case the DRAM starting address does not start at aligned addresses. The lower
address bits determine the byte enables for the first data double Dword. At the end of the DMA
transfer, extra data will be discarded and byte enables are calculated for the last 64-bit double
Dword. After the data is loaded into the buffer, the PCI starting address is evaluated and the buffer
is shifted byte wise to align the starting DRAM data with the starting PCI starting address.