Intel NETWORK PROCESSOR IXP2800 - Manual (Page 3)

Hardware Reference Manual 3
Contents
Contents
1 Introduction..................................................................................................................................25
1.1
About This Document .........................................................................................................25
1.2 Related Documentation ......................................................................................................25
1.3 Terminology ........................................................................................................................26
2 Technical Description .................................................................................................................27
2.1
Overview.............................................................................................................................27
2.2 Intel XScale
®
Core Microarchitecture .................................................................................30
2.2.1 ARM* Compatibility ................................................................................................30
2.2.2 Features.................................................................................................................30
2.2.2.1
Multiply/Accumulate (MAC)....................................................................30
2.2.2.2 Memory Management ............................................................................30
2.2.2.3 Instruction Cache ...................................................................................30
2.2.2.4 Branch Target Buffer..............................................................................31
2.2.2.5 Data Cache ............................................................................................31
2.2.2.6 Interrupt Controller .................................................................................31
2.2.2.7 Address Map..........................................................................................32
2.3 Microengines ......................................................................................................................33
2.3.1
Microengine Bus Arrangement ..............................................................................35
2.3.2 Control Store..........................................................................................................35
2.3.3 Contexts.................................................................................................................35
2.3.4 Datapath Registers ................................................................................................37
2.3.4.1
General-Purpose Registers (GPRs) ......................................................37
2.3.4.2 Transfer Registers .................................................................................37
2.3.4.3 Next Neighbor Registers........................................................................38
2.3.4.4 Local Memory .......................................................................................39
2.3.5 Addressing Modes .................................................................................................41
2.3.5.1
Context-Relative Addressing Mode .......................................................41
2.3.5.2 Absolute Addressing Mode ....................................................................42
2.3.5.3 Indexed Addressing Mode .....................................................................42
2.3.6 Local CSRs............................................................................................................43
2.3.7 Execution Datapath ...............................................................................................43
2.3.7.1
Byte Align...............................................................................................43
2.3.7.2 CAM .......................................................................................................45
2.3.8 CRC Unit................................................................................................................48
2.3.9 Event Signals.........................................................................................................49
2.4 DRAM .................................................................................................................................50
2.4.1
Size Configuration .................................................................................................50
2.4.2 Read and Write Access .........................................................................................51
2.5 SRAM .................................................................................................................................51
2.5.1
QDR Clocking Scheme ..........................................................................................52
2.5.2 SRAM Controller Configurations............................................................................52
2.5.3 SRAM Atomic Operations ......................................................................................53
2.5.4 Queue Data Structure Commands ........................................................................54
2.5.5 Reference Ordering ...............................................................................................54
2.5.5.1
Reference Order Tables ........................................................................54
2.5.5.2 Microengine Software Restrictions to Maintain Ordering .......................56