Intel NETWORK PROCESSOR IXP2800 - Manual (Page 328)

328 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
PCI Unit
never de-asserts it prior to receiving gnt_l[0] or de-asserts it after receiving gnt_l[0] without doing
a transaction. PCI Unit de-asserts req_l[0] for two cycles when it receives a retry or disconnect
response from the target.
9.2.6.2 PCI Commands
The following PCI transactions are not generated by PCI Unit as an initiator:
• PCI Lock Cycle
• Dual Address cycle
• Memory Write and Invalidate
9.2.6.3 Initiator Write Transactions
The following general rules apply to the write command transactions:
• If the PCI unit receives either a target retry response or a target disconnect response before all
of the write data has been delivered, it resumes the transaction at the first opportunity, using
the address of the first undeliverable data.
• If the PCI unit receives a master abort, it discards all of the write data from that transaction and
sets the status register (PCI_STATUS) received master abort bit, which, if enabled, interrupts
the Intel XScale ® core.
• If the PCI unit receives a target abort, it discards all of the remaining write data from that
transaction, if any, and sets the status registers (PCI_STATUS) received target abort bit, which,
if enabled, interrupts the Intel XScale ® core.
• The PCI unit can dessert frame_l prior to delivering all data due to the master latency timer, If
this occurs, it resumes the write at the first opportunity, using the address of the first
undeliverable data.
9.2.6.4 Initiator Read Transactions
The following general rules apply to the read command transactions:
• If the PCI unit receives a target retry, it repeats the transaction at the first opportunity until the
whole transaction is completed.
• If the PCI unit receives a master abort, it substitutes 0xFFFF FFFF for the read data and sets
the status register (PCI_STATUS) received master abort bit, which, if enabled, interrupts the
Intel XScale
®
core.
• If the PCI unit receives a target abort, it sets the status registers (PCI_STATUS) received target
abort bit, which, if enabled, interrupts the Intel XScale
®
core and does not try to get any more
read data. PCI unit will substitute 0xFFFF FFFF for the data which are not read and complete
the cycle.
9.2.6.5 Initiator Latency Timer
When the PCI unit begins PCI transaction as an initiator, asserting frame_l, it begins to decrement
its master latency timer. When the timer value reaches 0, the PCI unit checks the value of gnt_l[0].
If gnt_l[0] is de-asserted, the PCI unit de-asserts frame_l (if it is still asserted) at the earliest
opportunity. This is normally the next data phase for all transactions.