Intel NETWORK PROCESSOR IXP2800 - Manual (Page 373)

Hardware Reference Manual 373
Intel
®
IXP2800 Network Processor
Clocks and Reset
code is written in DRAM, PCI host writes 1 at bit [8] of Misc_Control register called Flash Alias
Disable (Reset value 0). The Alias Disable bit can be wired to the Intel XScale
® core gasket
directly so that gasket knows how to transform address 0 from the Intel XScale
®
core. After
writing 1 at Flash Alias Disable bit, host removes reset from the Intel XScale
®
core by writing 0 in
bit [0] of IXP_RESET0 register. The Intel XScale
®
core starts booting from address 0, which is
now directed by the gasket to DRAM.
10.5 Initialization
Refer to the Intel
®
IXP2800 Network Processor Hardware Initialization Reference Manual for
information about the initialization of all units of the IXP2800 Network Processor.