Intel NETWORK PROCESSOR IXP2800 - Manual (Page 294)

294 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Media and Switch Fabric Interface
The SPI-4.2 mode of the simplex configuration supports an LVTTL reverse path or status interface
clocked at up to 125 MHz or a DDR LVDS reverse path or status interface clocked at up to 500
MHz. The SPI-4.2 mode status interface consists of a clock signal and two data signals.
The CSIX-L1 protocol mode of the simplex configuration supports a full-duplex implementation
of the CSIX-L1 protocol, but no Data CFrames are transferred on the reverse path and the reverse
path is a quarter of the width of the forward path. The CSIX-L1 protocol mode supports a DDR
LVDS reverse path interface clocked at up to 500 MHz. The CSIX-L1 protocol mode reverse path
control interface consists of a clock signal, four data signals, a parity signal, and a start-of-frame
signal.
8.9.1.2 Hybrid Simplex Configuration
In the hybrid simplex configuration, data transfers and link-level flow control is supported via the
SPI-4.2 modes of the receiver and transmitter, as shown in
Figure 103 . Only the LVTTL SPI-4.2
status interface is supported in this configuration.
Virtual output queue flow control information (or other information) is delivered to the transmitter
via the CSIX-L1 protocol via an interface similar to the reverse path of the CSIX-L1 protocol mode
of the simplex configuration. Flow control for the CSIX-L1 CFrames is provided by an
asynchronous LVDS signal back to the fabric and not by the “ready bits” of the CSIX-L1 protocol.
The hybrid simplex configuration for a fabric interface may be especially useful to implementers
when an SPI-4.2 interface implementation is readily available. The CSIX-L1 protocol reverse path
may not need to operate at a clock rate as aggressive as the SPI-4.2 interface and, as such, may be
easier to implement than a full-rate data interface.
Figure 103. Hybrid Simplex Configuration
B2736-02
Network
Processor
Transmitter
Fabric
Receiver
SPI-4.2 LVTTL Reverse Path
CSIX Protocol DDR LVDS Reverse Path
DDR LVDS Flow Control
SPI-4.2 Forward Path