Intel NETWORK PROCESSOR IXP2800 - Manual (Page 69)

Hardware Reference Manual 69
Intel
®
IXP2800 Network Processor
Technical Description
2.8 Hash Unit
The IXP2800 Network Processor contains a Hash Unit that can take 48-, 64-, or 128-bit data and
produce a 48-, 64-, or a 128-bit hash index, respectively. The Hash Unit is accessible by the
Microengines and the Intel XScale
®
core, and is useful in doing table searches with large keys, for
example L2 addresses. Figure 14 is a block diagram of the Hash Unit.
Up to three hash indexes can be created using a single Microengine instruction. This helps to
minimize command overhead. The Intel XScale ® core can only do a single hash at a time.
A Microengine initiates a hash operation by writing the hash operands into a contiguous set of
S_TRANSFER_OUT registers and then executing the hash instruction. The Intel XScale
®
core
initiates a hash operation by writing a set of memory-mapped HASH_OP registers, which are built
in the Intel XScale ® core gasket, with the data to be used to generate the hash index. There are
separate registers for 48-, 64-, and 128-bit hashes. The data is written from MSB to LSB, with the
write to LSB triggering the Hash Operation. In both cases, the Hash Unit reads the operand into an
input buffer, performs the hash operation, and returns the result.
The Hash Unit uses a hard-wired polynomial algorithm and a programmable hash multiplier to
create hash indexes. Three separate multipliers are supported, one for 48-bit hash operations, one
for 64-bit hash operations and one for 128-bit hash operations. The multiplier is programmed
through Control registers in the Hash Unit.
The multiplicand is shifted into the hash array, 16 bits at a time. The hash array performs a
1’s-complement multiply and polynomial divide, using the multiplier and 16 bits of the
multiplicand. The result is placed into an output buffer register and also feeds back into the array.
This process is repeated three times for a 48-bit hash (16 bits x 3 = 48), four times for a 64-bit hash
(16 bits x 4 = 64), and eight times for a 128-bit hash (16 x 8 = 128). After the multiplicand has been
passed through the hash array, the resulting hash index is placed into a two-stage output buffer.
After each hash index is completed, the Hash Unit returns the hash index to the Microengines’
S_TRANSFER_IN registers, or the Intel XScale ® core HASH_OP registers. For Microengine
initiated hash operations, the Microengine is signaled after all the hashes specified in the
instruction have been completed.
For the Intel XScale ® core initiated hash operations, the Intel XScale ® core reads the results from
the memory-mapped HASH_OP registers. The addresses of Hash Results are the same as the
HASH_OP registers. Because of queuing delays at the Hash Unit, the time to complete an
operation is not fixed. The Intel XScale
®
core can do one of two operations to get the hash results.
• Poll the HASH_DONE register. This register is cleared when the HASH_OP registers are
written. Bit [0] of HASH_DONE register is set when the HASH_OP registers get the return
result from the Hash Unit (when the last word of the result is returned). The Intel XScale ® core
software can poll on HASH_DONE, and read HASH_OP when HASH_DONE is equal to
0x00000001.
• Read HASH_OP directly. The interface hardware will acknowledge the read only when the
result is valid. This method will result in the Intel XScale
® core stalling if the result is not
valid when the read happens.
The number of clock cycles required to perform a single hash operation equals: two or four cycles
through the input buffers, three, four or eight cycles through the hash array, and two or four cycles
through the output buffers. Because of the pipeline characteristics of the Hash Unit, performance is
improved if multiple hash operations are initiated with a single instruction rather than separate hash
instructions for each hash operation.