3 tbuf to spi-4 transfer, Tbuf to spi-4 transfer, 65 msf interface – Intel NETWORK PROCESSOR IXP2800 User Manual
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186
Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Microengines
Since data in RBUF or DRAM is arranged in LWBE order, it is swapped on the way into the TBUF
to make it truly big-endian, as shown in
. Again, the invalid bytes at the beginning of the
payload that starts at offset 3 and at the end-of-header at offset 2 is removed by the aligner on the
way out of TBUF.
4.5.2.3
TBUF to SPI-4 Transfer
shows how the MSF interface removes invalid bytes from TBUF data and transfers them
onto the SPI-4 interface in 16-bit (2-byte) chunks.
Figure 65. MSF Interface
A8946-01
To SPI-4 Interface
To
Serial
Link
offset 0
offset 1
offset 2
offset 3
offset 4
offset 5
LW0
Word to Byte conversion
Byte to bit-stream
conversion
4
3
h3 h2 h1
h1
h2
LW1
A15
A7
A8
A0
X
X
X
X
X
h1
h2
h3
h4
h5
h6
h7
h8
h9 h10 h11
h12 h13
X
X
X
X
X
X
X
X
X
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
h3
h4
h5
h6
h7
h8
h9
h10
h11
h12
h13
3
4
5
6
7
8
9
10
11
12
13
15
14
After removing the
invalid bytes,
data is packed in
two byte chunks.