Intel NETWORK PROCESSOR IXP2800 - Manual (Page 73)

Hardware Reference Manual 73
Intel
®
IXP2800 Network Processor
Technical Description
2.9.3.2 DMA Channel Operation
The DMA channel can be set up to read the first descriptor in SRAM, or with the first descriptor
written directly to the DMA channel registers. When descriptors and the descriptor list are in
SRAM, the procedure is as follows:
1. The DMA channel owner writes the address of the first descriptor into the DMA Channel
Descriptor Pointer register (DESC_PTR).
2. The DMA channel owner writes the DMA Channel Control register (CONTROL) with
miscellaneous control information and also sets the channel enable bit (bit 0). The channel
initial descriptor bit (bit 4) in the CONTROL register must also be cleared to indicate that the
first descriptor is in SRAM.
3. Depending on the DMA channel number, the DMA channel reads the descriptor block into the
corresponding DMA registers, BYTE_COUNT, PCI_ADDR, DRAM_ADDR, and
DESC_PTR.
4. The DMA channel transfers the data until the byte count is exhausted, and then sets the
channel transfer done bit in the CONTROL register.
5. If the end of chain bit (bit 31) in the BYTE_COUNT register is clear, the channel checks the
Chain Pointer value. If the Chain Pointer value is not equal to 0. it reads the next descriptor
and transfers the data (step 3 and 4 above). If the Chain Pointer value is equal to 0, it waits for
the Descriptor Added bit of the Channel Control register to be set before reading the next
descriptor and transfers the data (step 3 and 4 above). If bit 31 is set, the channel sets the
channel chain done bit in the CONTROL register and then stops.
6. Proceed to the Channel End Operation.
When single descriptors are written into the DMA channel registers, the procedure is as follows:
1. The DMA channel owner writes the descriptor values directly into the DMA channel registers.
The end of chain bit (bit 31) in the BYTE_COUNT register must be set, and the value in the
DESC_PTR register is not used.
2. The DMA channel owner writes the base address of the DMA transfer into the PCI_ADDR to
specify the PCI starting address.
3. When the first descriptor is in the BYTE_COUNT register, the DRAM_ADDR register must
be written with the address of the data to be moved.
4. The DMA channel owner writes the CONTROL register with miscellaneous control
information, along with setting the channel enable bit (bit 0). The channel initial descriptor in
register bit (bit 4) in the CONTROL register must also be set to indicate that the first descriptor
is already in the channel descriptor registers.
5. The DMA channel transfers the data until the byte count is exhausted, and then sets the
channel transfer done bit (bit 2) in the CONTROL register.
6. Since the end of the chain bit (bit 31) in the BYTE_CONT register is set, the channel sets the
channel chain done bit (bit 7) in the CONTROL register and then stops.
7. Proceed to the Channel End Operation.