Intel NETWORK PROCESSOR IXP2800 - Manual (Page 51)

Hardware Reference Manual 51
Intel
®
IXP2800 Network Processor
Technical Description
2.4.2 Read and Write Access
The minimum DRAM physical access length is 16 bytes. Software (and PCI) can read or write as
little as a single byte, however the time (and bandwidth) taken at the DRAMs is the same as for an
access of 16 bytes. Therefore, the best utilization of DRAM bandwidth will be for accesses that are
multiples of 16 bytes.
If ECC is enabled, writes of less than 8 bytes must do read-modify-writes, which take two 16-byte
time accesses (one for the read and one for the write).
2.5 SRAM
The IXP2800 Network Processor has four independent SRAM controllers, which each support
pipelined QDR synchronous static RAM (SRAM) and/or a coprocessor that adheres to QDR
signaling. Any or all controllers can be left unpopulated if the application does not need to use
them. SRAM are accessible by the Microengines, the Intel XScale ® core, and the PCI Unit
(external bus masters and DMA).
The memory is logically four bytes (32-bits) wide; physically the data pins are two bytes wide and
are double clocked. Byte parity is supported. Each of the four bytes has a parity bit, which is
written when the byte is written and checked when the data is read. There are byte-enables that
select which bytes to write for writes of less than 32 bits.
Each of the 4 QDR ports are QDR and QDRII compatible. Each port implements the “_K” and
“_C” output clocks and “_CQ” as an input and their inversions. (Note: the “_C” and “_CQ” clocks
are optional). Extensive work has been performed providing impedance controls within the
IXP2800 Network Processor for processor-initiated signals driving to QDR parts. Providing a
clean signaling environment is critical to achieving 200 – 250 MHz QDRII data transfers.
The configuration assumptions for the IXP2800 Network Processor I/O driver/receiver
development includes four QDR loads and the IXP2800 Network Processor. The IXP2800
Network Processor supports bursts of two SRAMs, but does not support bursts of four SRAMs.
The SRAM controller can also be configured to interface to an external coprocessor that adheres to
the QDR electricals and protocol. Each SRAM controller may also interface to an external
coprocessor through its standard QDR interface. This interface enables the cohabitation of both
SRAM devices and coprocessors to operate on the same bus. The coprocessor behaves as a
memory-mapped device on the SRAM bus.