Intel NETWORK PROCESSOR IXP2800 - Manual (Page 239)

Hardware Reference Manual 239
Intel
®
IXP2800 Network Processor
SHaC — Unit Expansion
The Hash Unit shares the Scratchpad’s Push Data FIFO. After each hash index is completed, the
index is placed into a three-stage output pipe and the Hash Unit sends a PUSH_DATA_REQ to the
Scratchpad to indicate that it has a valid hash index to put into the Push Data FIFO for transfer. The
Scratchpad issues a SEND_HASH_DATA signal, transfers the hash index to the Push Data FIFO,
and sends the data to the Arbiter.
For hash operations initiated by the Intel XScale
®
core, the core reads the results from its memory-
mapped Hash Result registers. The addresses of Hash Results are the same as the Hash Operand
registers. Because of queuing delays at the Hash Unit, the time to complete an operation is not
fixed. The Intel XScale
® core can do one of two operations to get the hash results:
• Poll the Hash Done register. This register is cleared when the Hash Operand registers are
written. Bit [0] of the Hash Done register is set when the Hash Result registers get the result
from the Hash Unit (when the last word of the result is returned). The Intel XScale
®
core
software can poll on Hash Done, and read Hash Result when Hash Done equals 0x00000001.
• Read Hash Result directly. The gasket logic acknowledges the read only when the result is
valid. The Intel XScale
®
core stalls if the result is not valid when the read happens.
The number of clock cycles required to perform a single hash operation equals: two or four cycles
through the input buffers, three, four, or eight cycles through the hash array, and two or four cycles
through the output buffers. With the pipeline characteristics of the Hash Unit, performance is
improved if multiple hash operations are initiated with a single instruction, rather than with
separate hash instructions for each hash operation.
7.1.3.2 Hash Algorithm
The hashing algorithm allows flexibility and uniqueness since it can be programmed to provide
different results for a given input. The algorithm uses binary polynomial multiplication and
division under modulo-2 addition. The input to the algorithm is a 48-, 64-, or 128-bit value.
The data used to generate the hash index is considered to represent the coefficients of an order-47,
order-63, or order-127 polynomial in x. The input polynomial (designated as A(x)) has the form:
Equation 1. (48-bit hash operation)
Equation 2. (64-bit hash operation)
Equation 3. (128-bit hash operation)
This polynomial is multiplied by a programmable hash multiplier using a modulo-2 addition. The
hash multiplier, M(x) is stored in Hash Unit CSRs and represents the polynomial.
Equation 4. (48-bit hash operation)
Equation 5. (64-bit hash operation)
Equation 6. (128-bit hash operation)
Since multiplication is performed using modulo-2 addition, the result is an order-94 polynomial, an
order-126 polynomial, or an order-254 polynomial with coefficients that are also 1 or 0. This
product is divided by a fixed generator polynomial given by:
A
48
x ( ) a
0
a
1
x a
2
x
2
… a
46
x
46
a
47
x
47
+ + + + + =
A
64
x ( ) a
0
a
1
x a
2
x
2
… a
62
x
62
a
63
x
63
+ + + + + =
A
128
x ( ) a
0
a
1
x a
2
x
2 … a
126
x
126
a
127
x
127
+ + + + + =
M
48
x ( ) m
0
m
1
x m
2
x
2 … m
46
x
46
m
47
x
47
+ + + + + =
M
64
x ( ) m
0
m
1
x m
2
x
2
… m
62
x
62
m
63
x
63
+ + + + + =
M
128
x ( ) m
0
m
1
x m
2
x
2 … m
126
x
126
m
127
x
127
+ + + + + =