Intel NETWORK PROCESSOR IXP2800 - Manual (Page 225)

Hardware Reference Manual 225
Intel
®
IXP2800 Network Processor
SHaC — Unit Expansion
SHaC — Unit Expansion
7
This section covers the operation of the Scratchpad, Hash Unit, and CSRs (SHaC).
7.1 Overview
The SHaC unit is a multifunction block containing Scratchpad memory and logic blocks used to
perform hashing operations and interface with the Intel XScale
®
core peripherals and control status
registers (CSRs) through the Advanced Peripheral Bus (APB) and CSR buses, respectively. The
SHaC also houses the global registers, as well as Reset logic.
The SHaC unit has the following features:
• Communication to Intel XScale
®
core peripherals, such as GPIOs and timers, through the
APB.
• Creation of hash indices of 48-, 64-, or 128-bit widths.
• Communication ring used by Microengines for interprocess communication.
• Third-option memory storage usable by Intel XScale ® core and Microengines.
• CSR bus interface to permit fast writes to CSRs, as well as standard read and writes.
• Push/Pull Reflector to transfer data from the Pull bus to the Push bus.
The CSR and Α RM* Advanced Peripheral Bus (APB) bus interfaces are controlled by the
Scratchpad state machine and will be addressed in the Scratchpad design detail section.
(See
Section 7.1.2 .)
Note: Detailed information about CSRs is contained in the Intel
®
IXP2400 and IXP2800 Network
Processor Programmer’s Reference Manual.
7.1.1 SHaC Unit Block Diagram
The SHaC unit contains two functional units: the Scratchpad and Hash Unit. Each will be described
in greater detail in the following sections. The CAP and APB interfaces are described as part of the
Scratchpad description.