Maxim Integrated DS33Z41 - Manual (Page 96)

DS33Z41 Quad IMUX Ethernet Mapper
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Register Name:
LI.THPMUU
Register Description: Serial Interface Transmit HDLC PMU Update Register
Register Address: 0D6h
Bit # 7 6 5 4 3 2 1 0
Name — — — — — — — TPMUU
Default 0 0 0 0 0 0 0 0
Bit 0: Transmit PMU Update (TPMUU). This signal causes the transmit cell/packet processor block performance
monitoring registers (counters) to be updated. A 0 to 1 transition causes the performance monitoring registers to
be updated with the latest data, and the counters reset (0 or 1). This update updates performance monitoring
counters for the Serial Interface.
Register Name:
LI.THPMUS
Register Description: Serial Interface Transmit HDLC PMU Update Status Register
Register Address: 0D7h
Bit # 7 6 5 4 3 2 1 0
Name — — — — — — — TPMUS
Default 0 0 0 0 0 0 0 0
Bit 0: Transmit PMU Update Status (TPMUS). This bit is set when the Transmit PMU Update is completed. This
bit is cleared when TPMUU is reset.