Maxim Integrated DS33Z41 - Manual (Page 72)

DS33Z41 Quad IMUX Ethernet Mapper
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Register Name: GL.TRQIE
Register Description: Global Transmit Receive Queue Interrupt Enable
Register Address: 0Ah
Bit # 7 6 5 4 3 2 1 0
Name — — — TQ1IE — — — RQ1IE
Default 0 0 0 0 0 0 0 0
Bit 4: Transmit Queue 1 Interrupt Enable (TQ1IE). Setting this bit to 1 enables an interrupt on TQ1IS.
Bit 0: Receive Queue 1 Interrupt Enable (RQ1IE). Setting this bit to 1 enables an interrupt on RQ1IS.
Register Name:
GL.TRQIS
Register Description: Global Transmit Receive Queue Interrupt Status
Register Address: 0Bh
Bit # 7 6 5 4 3 2 1 0
Name — — — TQ1IS — — — RQ1IS
Default 0 0 0 0 0 0 0 0
Bit 4: Transmit Queue 1 Interrupt Enable (TQ1IS). If this bit is set to 1, the Transmit Queue 1 has interrupt
status event. Transmit queue events are transmit queue crossing thresholds and queue overflows.
Bit 0: Receive Queue 1 Interrupt Status (RQ1IS). If this bit is set to 1, the Receive Queue 1 has interrupt status
event. Receive queue events are transmit queue crossing thresholds and queue overflows.
Register Name: GL.IBIE
Register Description: Global IMUX and BERT Interrupt Enable
Register Address: 0Ch
Bit # 7 6 5 4 3 2 1 0
Name — — — — — — IMUXIE BIE
Default 0 0 0 0 0 0 0 0
Bit 1: IMUX Interrupt Enable (IMUXIE). Setting this bit to 1 enables an interrupt on IIS.
Bit 0: BERT Interrupt Enable (BIE). Setting this bit to 1 enables an interrupt on BIS.
Register Name: GL.IBIS
Register Description: Global IMUX and BERT Interrupt Status
Register Address: 0Dh
Bit # 7 6 5 4 3 2 1 0
Name — — — — — — IIS BIS
Default 0 0 0 0 0 0 0 0
Bit 1: IMUX Interrupt Status (IIS). This bit is set to 1 if the IMUX has an enabled interrupt generating event.
Bit 0: BERT Interrupt Status (BIS). This bit is set to 1 if the BERT has an enabled interrupt generating event.