Maxim Integrated DS33Z41 - Manual (Page 162)

DS33Z41 Quad IMUX Ethernet Mapper
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Figure 12-2. TAP Controller State Diagram
12.2 Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When
the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO.
While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage towards the serial
output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS HIGH will move the
controller to the Update-IR state. The falling edge of that same JTCLK will latch the data in the instruction shift
register to the instruction parallel output. Instructions supported by the device and its respective operational binary
codes are shown in
Table 12-1 .
1
0
0
1
1 1
1
1
1
1 1
1 1
1 1
0 0
0 0
0
1
0 0
0 0
1
1
0 0
0 0
Select
DR-Scan
Capture DR
Shift DR
Exit DR
Pause DR
Exit2 DR
Update DR
Select
IR-Scan
Capture IR
Shift IR
Exit IR
Pause IR
Exit2 IR
Update IR
Test Logic
Reset
Run Test/
Idle
0