Maxim Integrated DS33Z41 - Manual (Page 3)

DS33Z41 Quad IMUX Ethernet Mapper
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8.14 E THERNET MAC..........................................................................................................................46
8.14.1 MII Mode .............................................................................................................................................47
8.14.2 RMII Mode ..........................................................................................................................................47
8.14.3 PHY MII Management Block and MDIO Interface ..............................................................................48
8.15 BERT .........................................................................................................................................48
8.15.1 BERT Features ...................................................................................................................................48
8.15.2 Receive Data Interface .......................................................................................................................49
8.15.3 Repetitive Pattern Synchronization.....................................................................................................49
8.15.4 Pattern Monitoring...............................................................................................................................50
8.15.5 Pattern Generation..............................................................................................................................50
8.16 T RANSMIT P ACKET P ROCESSOR ..................................................................................................52
8.17 R ECEIVE P ACKET P ROCESSOR ....................................................................................................53
8.18 X.86 E NCODING AND D ECODING ..................................................................................................55
8.19 C OMMITTED I NFORMATION R ATE C ONTROLLER ............................................................................58
9 DEVICE REGISTERS .......................................................................................................60
9.1 R EGISTER B IT M APS ....................................................................................................................61
9.1.1 Global Register Bit Map ......................................................................................................................61
9.1.2 Arbiter Register Bit Map......................................................................................................................62
9.1.3 BERT Register Bit Map.......................................................................................................................62
9.1.4 Serial Interface Register Bit Map ........................................................................................................63
9.1.5 Ethernet Interface Register Bit Map....................................................................................................65
9.1.6 MAC Register Bit Map ........................................................................................................................66
9.2 G LOBAL R EGISTER D EFINITIONS ..................................................................................................68
9.3 A RBITER R EGISTERS ...................................................................................................................81
9.3.1 Arbiter Register Bit Descriptions.........................................................................................................81
9.4 BERT R EGISTERS .......................................................................................................................82
9.5 S ERIAL I NTERFACE R EGISTERS ....................................................................................................89
9.5.1 Serial Interface Transmit and Common Registers..............................................................................89
9.5.2 Serial Interface Transmit Register Bit Descriptions ............................................................................89
9.5.3 Transmit HDLC Processor Registers..................................................................................................90
9.5.4 X.86 Registers ....................................................................................................................................97
9.5.5 Receive Serial Interface......................................................................................................................99
9.6 E THERNET I NTERFACE R EGISTERS .............................................................................................112
9.6.1 Ethernet Interface Register Bit Descriptions.....................................................................................112
9.6.2 MAC Registers..................................................................................................................................124
10 FUNCTIONAL TIMING....................................................................................................140
10.1 MII AND RMII I NTERFACES ........................................................................................................140
11 OPERATING PARAMETERS .........................................................................................142
11.1 T HERMAL C HARACTERISTICS .....................................................................................................143
11.2 MII I NTERFACE ..........................................................................................................................144
11.3 RMII I NTERFACE .......................................................................................................................146
11.4 MDIO I NTERFACE .....................................................................................................................148
11.5 T RANSMIT WAN I NTERFACE ......................................................................................................149
11.6 R ECEIVE WAN I NTERFACE ........................................................................................................150
11.7 SDRAM T IMING ........................................................................................................................151
11.8 M ICROPROCESSOR B US AC C HARACTERISTICS .........................................................................155
11.9 JTAG I NTERFACE T IMING ..........................................................................................................158
12 JTAG INFORMATION.....................................................................................................159
12.1 JTAG TAP C ONTROLLER S TATE M ACHINE D ESCRIPTION ...........................................................160
12.2 I NSTRUCTION R EGISTER ............................................................................................................162
12.2.1 SAMPLE:PRELOAD .........................................................................................................................163