Maxim Integrated DS33Z41 - Manual (Page 2)

DS33Z41 Quad IMUX Ethernet Mapper
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TABLE OF CONTENTS
1 DESCRIPTION....................................................................................................................7
2 FEATURE HIGHLIGHTS ....................................................................................................8
2.1 G ENERAL ......................................................................................................................................8
2.2 L INK A GGREGATION (I NVERSE M ULTIPLEXING ) ...............................................................................8
2.3 HDLC ...........................................................................................................................................8
2.4 C OMMITTED I NFORMATION R ATE (CIR) C ONTROLLER .....................................................................8
2.5 X.86 S UPPORT ..............................................................................................................................8
2.6 SDRAM I NTERFACE ......................................................................................................................9
2.7 MAC I NTERFACE ...........................................................................................................................9
2.8 M ICROPROCESSOR I NTERFACE ......................................................................................................9
2.9 T EST AND D IAGNOSTICS ................................................................................................................9
2.10 S PECIFICATIONS COMPLIANCE .....................................................................................................10
3 APPLICATIONS................................................................................................................11
4 ACRONYMS AND GLOSSARY........................................................................................12
5 MAJOR OPERATING MODES .........................................................................................13
6 BLOCK DIAGRAMS .........................................................................................................13
7 PIN DESCRIPTIONS.........................................................................................................14
7.1 P IN F UNCTIONAL D ESCRIPTION ....................................................................................................14
8 FUNCTIONAL DESCRIPTION..........................................................................................22
8.1 P ROCESSOR I NTERFACE ..............................................................................................................23
8.1.1 Read-Write/Data Strobe Modes..........................................................................................................23
8.1.2 Clear on Read.....................................................................................................................................23
8.1.3 Interrupt and Pin Modes......................................................................................................................23
8.2 C LOCK S TRUCTURE .....................................................................................................................24
8.2.1 Serial Interface Clock Modes..............................................................................................................26
8.2.2 Ethernet Interface Clock Modes .........................................................................................................26
8.3 R ESETS AND L OW -P OWER M ODES ...............................................................................................27
8.4 I NITIALIZATION AND C ONFIGURATION ............................................................................................28
8.5 G LOBAL R ESOURCES ...................................................................................................................28
8.6 P ER -P ORT R ESOURCES ...............................................................................................................28
8.7 D EVICE I NTERRUPTS ....................................................................................................................29
8.8 S ERIAL I NTERFACE ......................................................................................................................31
8.9 L INK A GGREGATION (IMUX).........................................................................................................31
8.9.1 Microprocessor Requirements............................................................................................................33
8.9.2 IMUX Command Protocol ...................................................................................................................34
8.9.3 Out of Frame (OOF) Monitoring..........................................................................................................36
8.9.4 Data Transfer ......................................................................................................................................36
8.10 C ONNECTIONS AND Q UEUES ........................................................................................................37
8.11 A RBITER .....................................................................................................................................38
8.12 F LOW C ONTROL ..........................................................................................................................39
8.12.1 Full-Duplex Flow Control.....................................................................................................................40
8.12.2 Half-Duplex Flow control.....................................................................................................................41
8.12.3 Host-Managed Flow control ................................................................................................................41
8.13 E THERNET I NTERFACE P ORT .......................................................................................................42
8.13.1 DTE and DCE Mode ...........................................................................................................................43