Maxim Integrated DS33Z41 - Manual (Page 127)

DS33Z41 Quad IMUX Ethernet Mapper
127 of 167
Register Name:
SU.MACMIIA
Register Description: MAC MII Management (MDIO) Address Register
Register Address: 0014h (indirect)
0014h:
Bit
# 31 30 29 28 27 26 25 24
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Default 0 0 0 0 0 0 0 0
0015h:
Bit
# 23 22 21 20 19 18 17 16
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Default 0 0 0 0 0 0 0 0
0016h:
Bit
# 15 14 13 12 11 10 09 08
Name PHYA4 PHYA3 PHYA2 PHYA1 PHYA0 MIIA4 MIIA3 MIIA2
Default
0 1 0 1 1 0 1 0
0017h:
Bit
# 07 06 05 04 03 02 01 00
Name MIIA1 MIIA0 Reserved Reserved Reserved Reserved MIIW MIIB
Default 1 1 0 0 0 0 0 0
Bits 15 to 11: PHY Address (PHYA4 to PHYA0). These 5 bits select one of the 32 available PHY address
locations to access through the PHY management (MDIO) bus.
Bits 10 to 6: MII Address (MIIA4 to MIIA0). These 5 bits are the address location within the PHY that is being
accessed.
Bit 1: MII Write (MIIW). Write this bit to 1 in order to execute a write instruction over the MDIO interface. Write the
bit to zero to execute a read instruction.
Bit 0: MII Busy (MIIB). This bit is set to 1 by the DS33Z41 during execution of a MII management instruction
through the MDIO interface, and is set to zero when the DS33Z41 has completed the instruction. The user should
read this bit and ensure that it is equal to zero prior to beginning a MDIO instruction.