Maxim Integrated DS33Z41 - Manual (Page 116)

DS33Z41 Quad IMUX Ethernet Mapper
116 of 167
Register Name:
SU.LPBK
Register Description: Ethernet Interface Loopback Control Register
Register Address: 14Fh
Bit
# 7 6 5 4 3 2 1 0
Name — — — — — — — QLP
Default
0 0 0 0 0 0 0 0
Bit 0: Queue Loopback Enable (QLP). If this bit is set to 1, data from the Ethernet Interface receive queue is
looped back to the transmit queue. Buffered data from the serial interface will remain until the loopback is
removed.
Register Name:
SU.GCR
Register Description: Ethernet Interface General Control Register
Register Address: 150h
Bit
# 7 6 5 4 3 2 1 0
Name — — — — CRCS H10S ATFLOW JAME
Default 0 0 0 0 0 0 1 0
Bit 3: CRCS. If this bit is zero (default), the received MAC or Ethernet Frame CRC is stripped before the data is
encapsulated and transmitted on the serial interface. Data received from the serial interface is decapsulated, a
CRC is recalculated and appended to the packet for transmission to the Ethernet interface. If this bit is set to 1,
the CRC is not stripped from received packets prior to encapsulation and transmission to the serial interface, and
data received from the serial interface is decapsulated directly. No CRC recalculation is performed on data
received from the serial interface. Note that the maximum packet size supported by the Ethernet interface is still
2016 (this includes the 4 bytes of CRC).
Bit 2: H10S. This bit controls the 10/100 selection for RMII and DCE Mode. When in RMII mode, setting this bit
to 1 will cause the MAC will operate at 100Mbps and setting this bit to zero will cause the MAC to operate at
10Mbps. When in DCE mode, the bit function is inverted; setting this bit to 1 will cause the MAC to operate at
10Mbps. In DTE and MII mode, the MAC determines the data rate from the incoming TX_CLK and RX_CLK.
Bit 1: Automatic Flow Control Enable (ATFLOW). If this bit is set to 1, automatic flow control is enabled based
on the connection receive queue size and high watermarks. Pause frames are sent automatically in full duplex
mode. The pause time must be programmed through
SU.MACFCR . The jam sequence will not be sent
automatically in half duplex mode unless the JAME bit is set. This bit is applicable only in software mode.
Bit 0: Jam Enable (JAME). If this bit is set to 1, a Jam sequence is sent for a duration of 4 bytes. This function is
only valid in half duplex mode, and will only function if Automatic Flow Control is disabled. Note that if the receive
queue size is less than receive high threshold, setting a JAME will JAM one received frame. If JAME is set and
the receiver queue size is higher than the high threshold, all received frames are jammed until the queue empties
below the threshold.
Note that SU.GCR is only valid in the software mode. In hardware mode, pins are used to control Automatic flow
control and 100/10-speed selection.