Maxim Integrated DS33Z41 - Manual (Page 32)

DS33Z41 Quad IMUX Ethernet Mapper
32 of 167
Figure 8-3. IMUX Interface to T1/E1 Transceivers
T1E1
T1E1
T1E1
T1E1
LIU
LIU
LIU
LIU
Framer
Framer
Framer
Framer
I
B
O
TSER
RSER
TSYNC
RSYNC
Line 1
IMUX
Ethernet Port
Arbiter
SDRAM
Interface
H
D
L
C
T1E1
T1E1
TCLKI
RCLKI
Figure 8-4. Diagram of Data Transmission with IMUX Operation
. . .
. . .
. . .
. . .
Sequence 01
L1 03
L2 03
L3 03
L4 03
L1 04
L2 04
L3 04
L4 04
L1 31
L2 31
L3 31
L4 31
L1 32
L2 32
L3 32
L4 32
s01
s01
s01
s01
xxxx
xxxx
xxxx
xxxx
. . .
. . .
. . .
. . .
Sequence 02
L1 03
L2 03
L3 03
L4 03
L1 04
L2 04
L3 04
L4 04
L1 31
L2 31
L3 31
L4 31
L1 32
L2 32
L3 32
L4 32
s02
s02
s02
s02
xxxx
xxxx
xxxx
xxxx
LINK 1
LINK 2
LINK 3
LINK 4 FRAM
ER IBO 128 Byte Sequence 01 128 Byte Sequence 02 . . .
. . . L1 03 L2 03 L3 03 L4 03 L1 04 L2 04 L3 04 L4 04 L1 31 L2 31 L3 31 L4 31 L1 32 L2 32 L3 32 L4 32 s01 s01 s01 s01 xxxx xxxx xxxx xxxx
Byte Sequence Detail
. . . N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+119 N+120 . . .
From TSER
Encapsulated
Packet Byte:
Data on IBO Bus
TSYNC:
Time
Sequence
Numbers
Signaling
Channel