Maxim Integrated DS33Z41 - Manual (Page 27)

DS33Z41 Quad IMUX Ethernet Mapper
27 of 167
8.3 Resets and Low-Power Modes
The external RST pin and the global reset bit in GL.CR1 create an internal global reset signal. The global reset
signal resets the status and control registers on the chip (except the GL.CR1. RST bit) to their default values and
resets all the other flops to their reset values. The device should be reset after all power supplies, SYSCLKI,
RX_CLK, and TX_CLK are stable. The processor bus output signals are also placed in high-impedance mode
when the
RST pin is active (low). The global reset bit ( GL.CR1. RST) stays set after a one is written to it, but is
reset to zero when the external RST pin is active or when a zero is written to it. Allow 5ms after initiating a reset
condition for the reset operation to complete.
The Serial Interface reset bit in LI.RSTPD resets all the status and control registers on the Serial Interface to their
default values, except for the LI.RSTPD. RST bit. The Serial Interface includes the HDLC encoder/decoder, X86
encoder and decoder and the corresponding serial port. The Serial Interface reset bit ( LI.RSTPD. RST) stays set
after a one is written to it, but is reset to zero when the global reset signal is active or when a zero is written to it.
Table 8-2. Reset Functions
RESET FUNCTION LOCATION COMMENTS
Hardware Device Reset RST Pin
Transition to a logic 0 level resets the
device.
Hardware JTAG Reset JTRST Pin Resets the JTAG test port.
Global Software Reset GL.CR1 Writing to this bit resets the device.
Serial interface Reset LI.RSTPD
Writing to this bit resets a Serial
Interface.
Queue Pointer Reset GL.C1QPR
Writing to this bit resets the Queue
Pointers.
There are several features in the DS33Z41 to reduce power consumption. The reset bit in the LI.RSTPD register
minimizes power usage in the Serial Interface. Additionally, the RST pin or GL.CR1 .RST bit may be held in reset
indefinitely to keep the device in a low-power mode. Note that exiting a reset condition requires re-initialization
and configuration. For the lowest possible standby current, clocks may be externally gated.