Maxim Integrated DS33Z41 - Manual (Page 68)

DS33Z41 Quad IMUX Ethernet Mapper
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9.2 Global Register Definitions
Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status,
framer interrupt status, IBO configuration, MCLK configuration, and BPCLK configuration. These registers are
preserved to provide code compatibility with the multiport devices in this product family. The global registers bit
descriptions are presented below.
Register Name:
GL.IDRL
Register Description: Global ID Low Register
Register Address: 00h
Bit
# 7 6 5 4 3 2 1 0
Name ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00
Default
0 0 1 1 0 0 0 0
Bit 7: ID07. Reserved for future use.
Bit 6: ID06. Reserved for future use.
Bit 5: ID05. If this bit is set the device contains a RMII interface.
Bit 4: ID04. If this bit is set the device contains a MII interface.
Bit 3: ID03. If this bit is set the device contains an Ethernet PHY.
Bits 2 to 0: ID03 to ID00. A three-bit count that is equal to 000b for the first die revision, and is incremented with
each successive die revision. May not match the two-letter die revision code on the top brand of the device.
Register Name:
GL.IDRH
Register Description: Global ID High Register
Register Address: 01h
Bit
# 7 6 5 4 3 2 1 0
Name ID15 ID14 ID13 ID12 ID11 ID10 ID09 ID08
Default
0 0 0 0 0 0 1 1
Bits 7 to 5: ID15 to ID13. Number of ports in the device – 1.
Bit 4: ID12. If this bit is set the device has LIU functionality.
Bit 3: ID11. If this bit is set the device has a framer.
Bit 2: ID10. Reserved for future use.
Bit 1: ID09. If this bit is set the device has HDLC or X.86 encapsulation.
Bit 0: ID08. If this bit is set the device has inverse multiplexing functionality.