Maxim Integrated DS33Z41 - Manual (Page 159)

DS33Z41 Quad IMUX Ethernet Mapper
159 of 167
12 JTAG INFORMATION
The device supports the standard instruction codes SAMPLE:PRELOAD, BYPASS, and EXTEST. Optional public
instructions included are HIGHZ, CLAMP, and IDCODE. The device contains the following as required by IEEE
1149.1 Standard Test Access Port and Boundary Scan Architecture.
Test Access Port (TAP)
TAP Controller
Instruction Register Bypass Register
Boundary Scan Register
Device Identification Register
The Test Access Port has the necessary interface pinsL:
JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin
descriptions for details. Refer to IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994 for details
about the Boundary Scan Architecture and the Test Access Port.
Figure 12-1. JTAG Functional Block Diagram
Boundary Scan
Register
Identification
Register
Bypass
Register
Instruction
Register
Test Access Port
Controller
Mux
Select
Tri-State
JTDI
10K
JTMS
10K
JTCLK JTRST
10K
JTDO