Feature highlights, General, Link aggregation (inverse multiplexing) – Maxim Integrated DS33Z41 User Manual

Page 8: Hdlc, Committed information rate (cir) controller, X.86 support, Eneral, Ggregation, Nverse, Ultiplexing

DS33Z41 Quad IMUX Ethernet Mapper

8 of 167

2 FEATURE

HIGHLIGHTS

2.1 General

• 169-pin, 14mm x 14mm CSBGA package

• 1.8V supply with 3.3V tolerant inputs and outputs

• IEEE 1149.1 JTAG boundary scan

• Software access to device ID and silicon revision

• Development support includes evaluation kit, driver source code, and reference designs

2.2 Link

Aggregation

(Inverse Multiplexing)

• Link aggregation for up to 4 T1/E1 Links

• 8.192Mbps IBO interface to Dallas Semiconductor Framers/Transceivers

• Differential delay compensation up to 7.75ms for the 4 T1/E1 links

• Handshaking protocol between local and distant end for establishment of aggregation

2.3 HDLC

• HDLC controller engine

• Compatible with polled or interrupt driven environments

• Programmable FCS insertion and extraction

• Programmable FCS type

• Supports FCS error insertion

• Programmable packet size limits (Minimum 64 bytes and maximum 2016 bytes)

• Supports bit stuffing/destuffing

• Selectable packet scrambling/descrambling (X

+1)

• Separate FCS errored packet and aborted packet counts

• Programmable inter-frame fill for transmit HDLC

2.4 Committed Information Rate (CIR) Controller

• CIR controller limits transmission of data from the Ethernet Interface to the Serial Interface.

• CIR granularity at 512kbps

• CIR Averaging for smoothing traffic peaks

2.5 X.86

Support

• Programmable X.86 address/control fields for transmit and receive

• Programmable 2-byte protocol (SAPI) field for transmit and receive

• 32 bit FCS

• Transmit Transparency processing - 7E is replaced by 7D, 5E

• Transmit Transparency processing – 7D replaced by 7D, 5D

• Receive rate adaptation (7D, DD) is deleted.

• Receive Transparency processing - 7D, 5E is replaced by 7E

• Receive Transparency processing – 7D, 5D is replaced by 7D

• Receive Abort Sequence the LAPS packet is dropped if 7D7E is detect

• Self-synchronizing X

+1 payload scrambling.

• Frame indication due to bad Address/Control/SAPI, FCS error, abort sequence or frame size longer

than preset max.