Maxim Integrated DS33Z41 - Manual (Page 28)

DS33Z41 Quad IMUX Ethernet Mapper
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8.4 Initialization and Configuration
EXAMPLE DEVICE INITIALIZATION SEQUENCE:
STEP 1: Reset the device by pulling the RST pin low or by using the software reset bits outlined in Section 8.3 .
Clear all reset bits. Allow 5 milliseconds for the reset recovery.
STEP 2: Check the Device ID in the GL.IDRL and GL.IDRH registers.
STEP 3: Configure the system clocks. Allow the clock system to properly adjust.
STEP 4: Initialize the entire remainder of the register space with 00h (or otherwise if specifically noted in the
register’s definition), including the reserved bits and reserved register locations.
STEP 5: Write FFFFFFFFh to the MAC indirect addresses 010Ch through 010Fh.
STEP 6: Setup connection in the GL.CON1 register.
STEP 7: Configure the Serial Port register space as needed.
STEP 8: Configure the Ethernet Port register space as needed.
STEP 9: Configure the Ethernet MAC indirect registers as needed.
STEP 10: Configure the external Ethernet PHYs through the MDIO interface.
STEP 11: Clear all counters and latched status bits.
STEP 12: Set Queue sizes in the Arbiter and reset the queue pointers for the Ethernet and Serial interfaces.
STEP 13: Enable Interrupts as needed.
STEP 14: Initiate link aggregation as discussed in Section 8.9 .
STEP 15: Begin handling interrupts and latched status events.
8.5 Global Resources
In order to maintain software compatibility with the multiport devices in the product family, a set of Global registers
are located at 0F0h-0FFh. The global registers include Global resets, global interrupt status, interrupt masking,
clock configuration, and the Device ID registers. See the Global Register Definitions in
Table 9-2 .
8.6 Per-Port Resources
Multi-port devices in this product family share a common set of global registers, BERT, and Arbiter. All other
resources are per-port.