Maxim Integrated DS33Z41 - Manual (Page 158)

DS33Z41 Quad IMUX Ethernet Mapper
158 of 167
11.9 JTAG Interface Timing
Table 11-14. JTAG Interface Timing
(VDD3.3 = 3.3V ±5%, VDD1.8 = 1.8V ±5%, Tj = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
JTCLK Clock Period t1 1000 ns
JTCLK Clock High:Low Time t2:t3 (Note 1) 50 500 ns
JTCLK to JTDI, JTMS Setup Time t4 2 ns
JTCLK to JTDI, JTMS Hold Time t5 2 ns
JTCLK to JTDO Delay t6 2 50 ns
JTCLK to JTDO HIZ Delay t7 2 50 ns
JTRST Width Low Time t8 100 ns
Note 1: Clock can be stopped high or low.
Figure 11-15. JTAG Interface Timing Diagram
JTCLK
t1
JTD0
t4 t5
t2 t3
t7
JTDI, JTMS,
JTRST
t6
JTRST
t8